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ltc1760 1 sn1760 1760is information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. final electrical specifications n smbus charger/selector for two smart batteries* n voltage and current accuracy within 0.2% of value reported by battery n simplifies construction of smart battery system manager n includes all smbus charger v1.1 safety features n supports autonomous operation without a host n smbus switching for dual batteries with alarm monitoring for charging battery at all times n pin programmable limits for maximum charge current and voltage improve safety n allows both batteries to discharge simultaneously into single load with low loss (ideal diode) n fast autonomous power path switching (<10 m s) n low loss simultaneous charging of two batteries n >95% efficient synchronous buck charger n ac adapter current limiting* maximizes charge rate n smbus accelerator improves smbus timing** n available in 48-lead tssop package applicatio s u features descriptio u dual smart battery system manager may 2003 the ltc ? 1760 smart battery system manager is a highly integrated level 3 battery charger and selector intended for products using dual smart batteries. three smbus inter- faces allow the ltc1760 to servo to the internal voltage and currents measured by the batteries while allowing an smbus host to monitor either batterys status. charging accuracy is determined by the batterys internal voltage and current measurement, typically better than 0.2%. a proprietary powerpath tm architecture supports simulta- neous charging or discharging of both batteries. typical battery run times are extended by up to 10%, while charging times are reduced by up to 50%. the ltc1760 automatically switches between power sources in less than 10 m s to prevent power interruption upon battery or wall adapter removal. the ltc1760 implements all elements of a version 1.1 smart battery system manager except for the genera- tion of composite battery information. an internal multi- plexer cleanly switches the smbus host to either of the two attached smart batteries without generating partial messages to batteries or smbus host. thermistors on both batteries are automatically monitored for tempera- ture and disconnection information (safetysignal). , ltc and lt are registered trademarks of linear technology corporation. n portable computers and instruments n standalone dual smart battery chargers n battery backup systems typical applicatio u time (minutes) battery current (ma) 3500 3000 2500 2000 1500 1000 500 0 3500 3000 2500 2000 1500 1000 500 0 1760 ta03 0 50 100 150 200 250 300 bat1 current bat2 current sequential dual bat1 current 100 minutes battery type: 10.8v li-ion (moltech ni2020) requested current = 3a requested voltage = 12.3v max charger current = 4.1a bat2 current dual battery charger/selector system architecture dual vs sequential charging powerpath is a trademark of linear technology corporation *u.s. patent no. 5,723,970 **u.s. patent no. 6,650,174 ltc1760 dc in system power smbus (host) 1760 ta01 safetysignal 1 smbus 1 safetysignal 2 smbus 2
ltc1760 2 sn1760 1760is voltage from dcin, scp, scn, clp, v plus , sw to gnd ................................... 32v/C0.3 v voltage from sch1, sch2 to gnd ................ 28v/C0.3 v voltage from boost to gnd ........................ 37v/ C0.3v csp, csn, bat1, bat2 to gnd ..................... 28v/C0.3v lopwr, dcdiv to gnd ................................ 10v/ C0.3v voltage from v cc2 , v dds to gnd .................... 7v/C0.3 v sda1, sda2, sda, scl1, scl2, scl, smbalert to gnd ........................................................ 7v/C0.3v mode to gnd ..................................... v cc2 +0.3v/C0.3v comp1 to gnd ............................................... 5v/ C0.3v operating ambient temperature (note 6) .... 0 c to 70 c operating junction temperature ...........C40 c to 125 c storage temperature .............................C65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c order part number t jmax = 125 c, q ja = 100 c/w LTC1760CFW absolute axi u rati gs w ww u package/order i for atio uu w (note 1) electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v dcin = 20v, v bat1 = 12v, v bat2 = 12v, v vdds = 3.3v, v vcc2 = 5.2v unless otherwise noted. consult ltc marketing for parts specified with wider operating temperature ranges. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 top view fw package 48-lead plastic tssop 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 sch2 gch2 gch1 sch1 tgate boost sw dcin v cc bgate pgnd comp1 clp csp csn v limit i limit th1b th1a smbalert th2a th2b mode v cc2 v plus bat2 bat1 scn scp gdco gdci gb1o gb1i gb2o gb2i lopwr v set i th i set dcdiv scl2 scl scl1 v dds sda2 sda sda1 gnd symbol parameter conditions min typ max units supply and reference dcin operating range dcin selected 6 28 v i ch0 dcin operating current not charging (dcin selected) (note 10) 1 1.5 ma i ch1 charging (dcin selected) (note 10) 1.3 2 ma i vcc2_ac1 v cc2 operating current ac present (note 11) 0.75 1 ma i vcc2_ac0 ac not present (note 11) 75 100 m a battery operating voltage range battery selected, powerpath function 6 28 v battery selected, charging function (note 2) 0 28 v i bat battery drain current battery selected, not charging, v dcin = 0v (note 10) 175 m a v plus diodes forward voltage: v fdc dcin to v plus i vcc = 10ma 0.8 v v fb1 bat1 to v plus i vcc = 0ma 0.7 v v fb2 bat2 to v plus i vcc = 0ma 0.7 v v fscn scn to v plus i vcc = 0ma 0.7 v uvlo undervoltage lockout threshold v plus ramping down, measured at v plus to gnd l 35v v vcc v cc regulator output voltage l 4.9 5.2 5.5 v v ldr v cc load regulation i vcc = 0ma to 10ma l 0.2 1 % switching regulator v tol voltage accuracy with respect to voltage reported by battery l C32 32 mv v chmin < requested voltage < v limit
ltc1760 3 sn1760 1760is electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v dcin = 20v, v bat1 = 12v, v bat2 = 12v, v vdds = 3.3v, v vcc2 = 5.2v unless otherwise noted. symbol parameter conditions min typ max units i tol current accuracy with respect to current reported by battery 4mv/r sense < requested current < i limit (min) (note 12) r ilimit = 0 (short to gnd) l C2 2 ma r ilimit = 10k 1% l C4 4 ma r ilimit = 33k 1% l C8 8 ma r ilimit = open (or short i limit to v cc2 ) l C8 8 ma f 0sc regulator switching frequency 255 300 345 khz f do regulator switching frequency in low duty cycle 3 99% 20 25 khz dropout mode dc max regulator maximum duty cycle 99 99.5 % i max maximum current sense threshold v ith = 2.2v 140 155 190 mv i sns ca1 input bias current v csp = v csn > 5v 150 m a cmsl ca1/i 1 input common mode low 0 v cmsh ca1/i 1 input common mode high v dcin C 0.2 v v cl1 cl1 turn-on threshold 95 100 105 mv l 94 100 108 mv tgate transition time: tg t r tgate rise time c load = 3300pf, 10% to 90% 50 90 ns tg t f tgate fall time c load = 3300pf, 10% to 90% 50 90 ns bgate transition time: bg t r bgate rise time c load = 3300pf, 10% to 90% 50 90 ns bg t f bgate fall time c load = 3300pf, 10% to 90% 40 80 ns trip points v tr dcdiv/lopwr threshold v dcdiv or v lopwr falling l 1.166 1.19 1.215 v v thys dcdiv/lopwr hysteresis voltage v dcdiv or v lopwr rising 30 mv i bvt dcdiv/lopwr input bias current v dcdiv or v lopwr = 1.19v 20 200 na v tsc short-circuit comparator threshold v scp C v scn , v cc 3 5v l 90 100 115 mv v fto fast power path turn-off threshold v dcdiv rising from v cc 6 7 7.9 v v ovsd overvoltage shutdown threshold as a v set rising from 0.8v until tgate and bgate 107 % percent of programmed charger voltage stop switching dacs i res i dac resolution guaranteed monotonic 10 bits i dac pulse period: t ip normal mode 61015 m s t ilow wake-up mode 50 ms charging current granularity r ilimit = (short i limit to gnd) 1 ma r ilimit = 10k 1% 2 ma r ilimit = 33k 1% 4 ma r ilimit = open (or short i limit to v cc2 )4ma i wake_up wake-up charging current (note 5) 60 80 100 ma i limit charging current limit r ilimit = 0 (short i limit to gnd) l 980 1000 1070 ma r ilimit = 10k 1% l 1960 2000 2140 ma r ilimit = 33k 1% l 2490 3000 3210 ma r ilimit = open (or short i limit to v cc2 ) l 3920 4000 4280 ma v res v dac resolution guaranteed monotonic (5v < v bat < 25v) 11 bits
ltc1760 4 sn1760 1760is the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v dcin = 20v, v bat1 = 12v, v bat2 = 12v, v vdds = 3.3v, v vcc2 = 5.2v unless otherwise noted. electrical characteristics v step v dac granularity 16 mv v limit charging voltage limit r vlimit = 0 (short v limit to gnd) l 8400 8432 8464 mv (note 7) r vlimit = 10k 1% l 12608 12640 12672 mv r vlimit = 33k 1% l 16832 16864 16896 mv r vlimit = 100k 1% l 21024 21056 21088 mv r vlimit = open (or short v limit to v cc2 )(note 13) l 32768 mv charge mux switches t onc gch1/gch2 turn-on time v gchx C v schx > 3v, c load = 3000pf 5 10 ms t offc gch1/gch2 turn-off time v gchx C v schx < 1v, from time of 15 m s v csn < v batx C 30mv, c load = 3000pf v con ch gate clamp voltage i load = 1 m a gch1 v gch1 C v sch1 5 5.8 7 v gch2 v gch2 C v sch2 5 5.8 7 v v coff ch gate off voltage i load =10 m a gch1 v gch1 C v sch1 C0.8 C0.4 0 v gch2 v gch2 C v sch2 C0.8 C0.4 0 v v toc ch switch reverse turn-off voltage v batx C v csn , 5v v batx 28v l 52040 mv v fc ch switch forward regulation voltage v csn C v batx , 5v v batx 28v l 15 35 60 mv gch1/gch2 active regulation: v gchx C v schx = 1.5v i oc(src) max source current C2 m a i oc(snk) max sink current 2 m a v chmin batx voltage below which 3.5 4.7 v charging is inhibited (does not apply to wake-up mode) powerpath switches t dly blanking period after uvlo trip switches held off 250 ms t ppb blanking period after lopwr trip switches in 3-diode mode 1 sec t onpo gb1o/gb2o/gdco turn-on time v gs < C3v, from time of battery/dc l 510 m s removal, or lopwr indication, c load = 3000pf t offpo gb1o/gb2o/gdco turn-off time v gs > C1v, from time of battery/dc l 37 m s removal, or lopwr indication, c load = 3000pf v pono output gate clamp voltage i load = 1 m a gb1o highest (v bat1 or v scp ) C v gb1o 4.75 6.25 7 v gb2o highest (v bat2 or v scp ) C v gb2o 4.75 6.25 7 v gdco highest (v dcin or v scp ) C v gdco 4.75 6.25 7 v v poffo output gate off voltage i load = C25 m a gb1o highest (v bat1 or v scp ) C v gb1o 0.18 0.25 v gb2o highest (v bat2 or v scp ) C v gb2o 0.18 0.25 v gdco highest (v dcin or v scp ) C v gdco 0.18 0.25 v v top powerpath switch reverse v scp C v batx or v scp C v dcin l 52060 mv turn-off voltage 6v v scp 28v v fp powerpath switch forward v batx C v scp or v dcin C v scp l 02550 mv regulation voltage 6v v scp 28v gdci/gb1i/gb2i active regulation: (note 3) i op(src) source current C4 m a i op(snk) sink current 75 m a symbol parameter conditions min typ max units
ltc1760 5 sn1760 1760is electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v dcin = 20v, v bat1 = 12v, v bat2 = 12v, v vdds = 3.3v, v vcc2 = 5.2v unless otherwise noted. symbol parameter conditions min typ max units t onpi gate b1i/b2i/dci turn-on time v gs < C3v, c load = 3000pf (note 4) 300 m s t offpi gate b1i/b2i/dci turn-off time v gs > C1v, c load = 3000pf (note 4) 10 m s v poni input gate clamp voltage i load = 1 m a gb1i highest (v bat1 or v scp ) C v gb1i 4.75 6.7 7.5 v gb2i highest (v bat2 or v scp ) C v gb2i 4.75 6.7 7.5 v gdci highest (v dcin or v scp ) C v gdci 4.75 6.7 7.5 v v poffi input gate off voltage i load = C25 m a gb1i highest (v bat1 or v scp ) C v gb1i 0.18 0.25 v gb2i highest (v bat2 or v scp ) C v gb2i 0.18 0.25 v gdci highest (v dcin or v scp ) C v gdci 0.18 0.25 v thermistor thermistor trip c load(max) = 300pf (note 9) l 95 100 105 k w (cold-range/over-range) r1a = r2a = 1130 w 1% r1b = r2b = 54900 w 1% thermistor trip c load(max) = 300pf (note 9) l 28.5 30 32.5 k w (ideal-range /cold-range) r1a = r2a = 1130 w 1% r1b = r2b = 54900 w 1% thermistor trip c load(max) = 300pf (note 9) l 2.85 3 3.15 k w (hot-range /ideal-range) r1a = r2a = 1130 w 1% r1b = r2b = 54900 w 1% thermistor trip c load(max) = 300pf (note 9) l 425 500 575 w (under-range /hot-range) r1a = r2a = 1130 w 1% r1b = r2b = 54900 w 1% logic levels scl/scl1/scl2/sda/sda1/ l 0.8 v sda2 input low voltage (v il ) scl/scl1/scl2/sda/sda1/ l 2.1 v sda2 input high voltage (v ih ) scl/scl1/scl2/sda/sda1/ v sda , v scl , v sda1 , v scl1 , l C5 5 m a sda2 input leakage current v sda2 , v scl2 = 0.8v scl/scl1/scl2/sda/sda1/ v sda , v scl , v sda1 , v scl1 , v sda2 , l C5 5 m a sda2 input leakage current v scl2 = 2.1v i pullup scl1/sda1/scl2/sda2 pull-up v scl1 = v sda1 = v scl2 = v sda2 = 0.4v 165 220 350 m a current when not connected to v vcc2 = 4.85v and 5.55v (current is through smbus host. internal series resistor and schottky to v cc2 ) scl1/sda1/scl2/sda2 v sda1 , v scl1 , v sda2 , v scl2 = 0.8v l 300 w series impedance to host smbus. scl/sda output low voltage (v ol ). i pullup = 350 m a l 0.4 v ltc1760 driving the pin. scl1/sda1/scl2/sda2 pullup i pullup internal to ltc1760 l 0.4 v output low voltage (vol). ltc1760 driving the pin with battery smbus not connected to host smbus. scl1/sda1/scl2/sda2 i pullup = 350 m a on host side l 0.4 v output low voltage (v ol ). ltc1760 driving the pin with battery smbus connected to host smbus
ltc1760 6 sn1760 1760is electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v dcin = 20v, v bat1 = 12v, v bat2 = 12v, v vdds = 3.3v, v vcc2 = 5.2v unless otherwise noted. note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2. battery voltage must be adequate to drive gates of power path p-channel fet switches. this does not affect charging voltage of the battery, which can be zero volts during wake-up charging. note 3. dcin, bat1, bat2 are held at 12v and gdci, gb1i, gb2i are forced to 10.5v. scp is set at 12v to measure source current at gdci, gb1i and gb2i. scp is set at 11.9v to measure sink current at gdci, gb1i and gb2i. note 4. extrapolated from testing with c l = 50pf. symbol parameter conditions min typ max units scl/scl1/scl2/sda/sda1/ sda2/ v vcc2 = 0v, v vdds = 0v, l 2ua smbalert power down leakage. v scl , v scl1 , v scl2 , v sda , v sda1 , v sda2 , v smbalert = 5.5v smbalert output low voltage (v ol )i pullup = 500 m a l 0.4 v smbalert output pull-up current v smbalert = 0.4v 3.5 10 17.5 m a v il_vdds v dds input low voltage (v il ) l 1.5 v v ih_vdds v dds input high voltage (v ih ) l 2.6 v v dds operating voltage l 3 5.5 v v dds operating current v scl , v sda = v vdds , v vdds = 5v 18 m a v il_mode mode input low voltage (v il )v vcc2 = 4.85v l v vcc2 ? 0.3 v v ih_mode mode input high voltage (v ih )v vcc2 = 4.85v l v vcc2 ? 0.7 v mode input current (i ih ) mode = v vcc2 ? 0.7v, v vcc2 = 4.85v l C1 1 m a mode input current (i il ) mode = v vcc2 ? 0.3v, v vcc2 = 4.85v l C1 1 m a charger timing t timeout timeout for wake-up charging and l 140 175 210 sec controlled charging. t query sampling rate used by the ltc1760 to 1 sec update charging parameters. smbus timing scl serial-clock high period(t high ) at i pullup = 350 m a, c load = 150pf (note 8) l 4 m s scl serial-clock low period (t low ) at i pullup = 350 m a, c load = 150pf (note 8) l 4.7 m s sda/scl rise time(t r )c load = 150pf, rpu = 9.31k (note 8) l 1000 ns sda/scl fall time(t f )c load = 150pf, rpu = 9.31k (note 8) l 300 ns smbus accelerator trip voltage range l 0.8 1.42 v start-condition setup time(t su:sta ) l 4.7 m s start-condition hold time(t hd:sta ) l 4 m s sda to scl rising-edge l 250 ns setup time(t su:dat ) sda to scl falling-edge hold time, l 300 ns slave clocking in data (t hd:dat ) t timeout_smb the ltc1760 will release the smbus l 25 35 ms and terminate the current master or slave command if the command is not completed before this time note 5. accuracy dependent upon external sense resistor and compensation components. note 6. the ltc1760c is guaranteed to meet specified performance from 0 c to 70 c and is designed, characterized and expected to meet specified performance at C40 c and 85 c, but is not tested at these extended temperature limits. note 7. charger servos to the value reported by a voltage() query. this is the internal cell voltage measured by the battery electronics and may be lower than the terminal voltage. see operation section 3.6 for more information.
ltc1760 7 sn1760 1760is typical perfor a ce characteristics uw efficiency vs charging current dual battery charge time vs sequential battery charging dual battery discharge time vs sequential battery discharge i out (a) 0 0 efficiency (%) 10 30 40 50 100 70 0.025 0.10 1960 g14 20 80 90 60 0.50 2.5 4.0 time (minutes) battery current (ma) 3500 3000 2500 2000 1500 1000 500 0 3500 3000 2500 2000 1500 1000 500 0 1960 g10 0 50 100 150 200 250 300 bat1 current bat2 current sequential dual bat1 current 100 minutes battery type: 10.8v li-ion (moltech ni2020) requested current = 3a requested voltage = 12.3v max charger current = 4.1a bat2 current time (minutes) 0 battery voltage (v) 120 12.0 11.0 10.0 9.0 8.0 12.0 11.0 10.0 9.0 8.0 1960 g12 20 180 40 60 80 100 140 160 bat1 voltage bat1 voltage dual sequential bat2 voltage bat2 voltage battery type: 10.8v li-ion(moltech ni2020) load current = 3a 11 minutes electrical characteristics note 8. c load is the combined capacitance on the hosts smbus connection and the selected batterys smbus connection. note 9. c load_max is the maximum allowed combined capacitance on thxa, thxb and the batterys safetysignalx connections. note 10. does not include current supplied by v cc to v cc2 (i vcc2_ac1 or i vcc2_ac0 ) note 11. measured with thermistors not present, r vilim and r ilim removed and smbalert = 1. see applications information section: calculating ic operating current for example on how to calculate total ic operating current. note 12. requested currents below 44mv/r sense may not servo correctly due to charger offsets. the charging current for requested currents below 4mv/r sense will be between 4mv/r sense and (requested curent C 8ma). refer to applications information: setting charger output current limit for values of r sense . note 13. this limit is greater than the absolute maximum for the charger. therefore, there is no effective limitation for the voltage when this option is selected. load dump time (ms) ? 2 bat1 voltage (v) 14 12 10 8 6 4 2 0 1960 g05 4 2 10 12 14 16 0 68 v in = 20v vdac = 12.29v idac = 3000ma load current = 1a t a = 25 c bat1 output load connected load disconnected charge current (ma) 0 bat1 voltage (v) 4000 1960 g06 1000 2000 3000 12.4 12.3 12.2 12.1 12.0 11.9 11.8 11.7 11.6 v in = 20v vdac = 12.288v idac = 4000ma t a = 25 c load regulation dual charging batteries with different charge state bat2 voltage bat2 current bat1 current bat1 voltage bat1 initial capacity = 0% bat2 initial capacity = 90% programmed charger current = 3a programmed charger voltage = 16.8v time (minutes) 0 battery voltage (v) 120 1760 g07 40 80 160 17.0 16.5 16.0 15.5 15.0 14.5 14.0 13.5 20 60 100 140 battery current (ma) 3500 3000 2500 2000 1500 1000 500 0
ltc1760 8 sn1760 1760is input power related scn (pin 4): powerpath current sensing negative input. this pin should be connected directly to the bottom (output side) of the low valued resistor in series with the three powerpath switch pairs, for detecting short-circuit current events. also powers ltc1760 internal circuitry when all other sources are absent. scp (pin 5): powerpath current sensing positive input. this pin should be connected directly to the top (switch side) of the low valued resistor in series with the three powerpath switch pairs, for detecting short-circuit cur- rent events. gdco (pin 6): dcin output switch gate drive. together with gdci, this pin drives the gate of the p-channel switch in series with the dcin input switch. gdci (pin 7): dcin input switch gate drive. together with gdco, this pin drives the gate of the p-channel switch connected to the dcin input. typical perfor a ce characteristics uw time ( s) 16 15 14 13 12 11 10 9 8 7 6 load voltage (v) 1960 g02 50 ?0 ?0 ?0 0 10 20 30 40 50 ?0 c load = 20 f i load = 0.8a t a = 25 c lopwr threshold power path switching 1 and 2 uu u pi fu ctio s gb1o (pin 8): bat1 output switch gate drive. together with gb1i, this pin drives the gate of the p-channel switch in series with the bat1 input switch. gb1i (pin 9): bat1 input switch gate drive. together with gb1o, this pin drives the gate of the p-channel switch connected to the bat1 input. gb2o (pin 10): bat2 output switch gate drive. together with gb2i, this pin drives the gate of the p-channel switch in series with the bat2 input switch. gb2i (pin 11): bat2 input switch gate drive. together with gb2o, this pin drives the gate of the p-channel switch connected to the bat2 input. clp (pin 36): this is the positive input to the supply current limiting amplifier cl1. the threshold is set at 100mv above the voltage at the dcin pin. when used to limit supply current, a filter is needed to filter out the switching noise.
ltc1760 9 sn1760 1760is boost (pin 43): supply to topside floating driver. the bootstrap capacitor is returned to this pin. voltage swing at this pin is from a diode drop below v cc to (dcin + v cc ). tgate (pin 44): drives the gate of the top external mosfet of the battery charger buck converter. sch1 (pin 45), sch2 (pin 48): charger mux switch source returns. these two pins are connected to the sources of q3/q4 and q9/q10 (see typical applications). a small pull-down current source returns these nodes to 0v when the switches are turned off. gch1 (pin 46), gch2 (pin 47): charger mux switch gate drives. these two pins drive the gates of the back-to-back n-channel switch pairs, q3/q4 and q9/q10, between the charger output and the two batteries (see typical applica- tions) external power supply pins v plus (pin 1): supply. the v plus pin is connected via four internal diodes to the dcin, scn, bat1, and bat2 pins. bypass this pin with a 0.1 m f capacitor and a 1 m f capacitor. see typical applications for complete circuit. bat1 (pin 3), bat2 (pin 2): these two pins are the inputs from the two batteries for power to the ltc1760. lopwr (pin 12): lopwr comparator input from exter- nal resistor divider connected from scn to gnd. if the voltage at lopwr pin is lower than the lopwr com- parator threshold, then system power has failed and power is autonomously switched to a higher voltage source, if available. dcdiv (pin 16): dcdiv comparator input from external resistor divider connected from dcin to gnd. if the voltage at dcdiv pin is above the dcdiv comparator threshold, then the ac_present bit is set and the wall adapter power is considered to be adequate to charge the batteries. if dcdiv is taken more than 1.8v above v cc , then all of the power path switches are latched off until all power is removed. dcin (pin 41): supply. external dc power source. a 0.1 m f bypass capacitor must be connected to this pin as close as possible. no series resistance is allowed, since the adapter current limit comparator input is also this pin. uu u pi fu ctio s battery charging related v set (pin 13): the tap point of a programmable resistor divider which provides battery voltage feedback to the charger. a capacitor from csn to v set and one from v set to gnd provide necessary compensation and filtering for the voltage loop. i th (pin 14): this is the control signal of the inner loop of the current mode pwm. higher i th corresponds to higher charging current in normal operation. a capacitor of at least 0.1 m f to gnd filters out pwm ripple. typical full- scale output current is 30 m a. nominal voltage range for this pin is 0v to 2.4v. i set (pin 15): a capacitor from i set to gnd is required to filter higher frequency components from the delta-sigma idac. i limit (pin 32): an external resistor (r ilimit ) is connected between this pin and gnd. the value of the external resistor programs the range and resolution of the pro- grammed charger current. v limit (pin 33): an external resistor (r vlimit )is connected between this pin and gnd. the value of the external resistor programs the range and resolution of the voltage dac. csn (pin 34): current amplifier ca1 input. connect this to the common output of the charger mux switches. csp (pin 35): current amplifier ca1 input. this pin and the csn pin measure the voltage across the sense resistor, r sense , to provide the instantaneous current signals re- quired for both peak and average current mode operation. comp1 (pin 37): this is the compensation node for the amplifier cl1. a capacitor is required from this pin to gnd if input current amplifier cl1 is used. at input adapter current limit, this node rises to 1v. by forcing comp1 to gnd, amplifier cl1 will be defeated (no adapter current limit). comp1 can source 10 m a. bgate (pin 39): drives the gate of the bottom external mosfet of the battery charger buck converter. sw (pin 42): connected to source of top external mosfet switch. used as reference for top gate driver.
ltc1760 10 sn1760 1760is internal power supply pins v dds (pin 20): power supply for smbus accellerators. also used in conjunction with mode pin to modify ltc1760 operating mode. gnd (pin 24): ground for low power circuitry. v cc2 (pin 25): the v cc2 power supply is used primarily to power internal logic circuitry. must be connected to v cc . pgnd (pin 38): high current ground return for bgate driver. v cc (pin 40): internal regulator output. bypass this output with at least a 2 m f to 4.7 m f capacitor. do not use this regulator output to supply external circuitry. sbs interface pins scl2 (pin 17): smbus clock signal to smart battery 2. do not connect to an external pull-up. the ltc1760 connects this pin to an internal pull-up (i pullup ) when required. scl (pin 18): smbus clock signal to smbus host. also used to determine flashing rate for stand-alone charge indicators. requires an external pullup to v dds (normal smbus operating mode). connected to internal smbus accelerator. scl1 (pin 19): smbus clock signal to smart battery 1. do not connect to an external pull-up. the ltc1760 connects this pin to an internal pull-up (i pullup ) when required. sda2 (pin 21): smbus data signal to smart battery 2. do not connect to an external pull-up. the ltc1760 connects this pin to an internal pull-up (i pullup ) when required. sda (pin 22): smbus data signal to smbus host. also used to indicate charging status of battery 2. requires an external pullup to v dds . connected to internal smbus accelerator. sda1 (pin 23): smbus data signal to smart battery 1. do not connect to an external pull-up. the ltc1760 connects this pin to an internal pull-up (i pullup ) when required. mode (pin 26): used in conjunction with v dds to allow scl, sda and smbalert to indicate charging status. may also be used as a hardware charge inhibit. th2b (pin 27): thermistor force/sense connection to smart battery 2 safetysignal. connect to battery 2 ther- mistor through resistor network shown in typical appli- cation. th2a (pin 28): thermistor force/sense connection to smart battery 2 safetysignal. connect to battery 2 ther- mistor through resistor network shown in typical appli- cation. smbalert (pin 29): active low interrupt pin. signals smbus host that there has been a change of status in battery or ac presence. open drain with weak current source pull-up to v cc2 (with schottky to allow it to be pulled to 5v externally). also used to indicate charging status of battery 1. th1a (pin 30): thermistor force/sense connection to smart battery 1 safetysignal. connect to battery 1 ther- mistor through resistor network shown in typical appli- cation. th1b (pin 31): thermistor force/sense connection to smart battery 1 safetysignal. connect to battery 1 ther- mistor through resistor network shown in typical appli- cation. uu u pi fu ctio s
ltc1760 11 sn1760 1760is block diagra w short circuit sequencer 10-bit ? s current dac limit decoder powerpath controller smbus interface charge + + 11-bit ? s voltage dac 100 100mv swb1 driver charge pump swb2 driver swdc driver csn + on + on dcin gch1 sch2 gch2 sch1 tgate pgnd bgate sw bat1 gnd dcdiv lopwr v cc v cc2 dcin dcin v set v plus bat2 oscillator low drop detect t on boost bgate v cc pwm logic + + + + q s r 100mv clp + 40mv + 15 scn gb1i gb1o gb2i gb2o gdci gdco scp scn csp th2b th2a th1b th1a csn i set ca1 3k 3k 0.8v buffered i th g m = 1.4m g m = 0.4m g m = 1.4m i rev i cmp i th comp1 csp-csn 3k 36 38 39 42 44 43 13 41 16 12 40 24 25 1 2 3 48 47 45 46 9 8 11 10 76 37 14 5 4 mode 26 30 31 28 27 15 35 34 cl1 ca2 v cc regulator safety signal decoder 1.19v 0.86v csn 0v 400k ea 0.8v ac_present i limit 32 v limit 33 1760 bd 3mv sda2 scl2 sda1 scl1 sda scl v dds v cc2 18 22 19 23 17 21 20 smbalert 29 10 a + + +
ltc1760 12 sn1760 1760is u u table of co te ts (for operation section) 1 overview ...................................................................................................................... ........................................................................ 13 2 the smbus interface ........................................................................................................... ................................................................ 13 2.1 smbus interface overview .................................................................................................... ........................................................... 13 2.2 data bit definition of supported smbus functions. ........................................................................... .............................................. 14 2.3 description of supported smbus functions .................................................................................... ................................................ 16 2.3.1 batterysystemstate() ('h01) ............................................................................................... ......................................................... 16 2.3.2 batterysystemstatecont() ('h02) ........................................................................................... ...................................................... 17 2.3.3 batterysysteminfo() ('h04) ................................................................................................ .......................................................... 18 2.3.4 ltc() ('h3c) .............................................................................................................. ................................................................... 19 2.3.5 batterymode() ('h03) ...................................................................................................... ............................................................. 19 2.3.6 voltage() ('h09) .......................................................................................................... ................................................................. 19 2.3.7 current() ('h0a) .......................................................................................................... .................................................................. 20 2.3.8 chargingcurrent() ('h14) .................................................................................................. ........................................................... 20 2.3.9 chargingvoltage() ('h15) .................................................................................................. ........................................................... 20 2.3.10 alarmwarning() ('h16) .................................................................................................... ............................................................ 20 2.3.11 alertresponse() .......................................................................................................... ................................................................. 21 2.4 smbus dual port operation ................................................................................................... .......................................................... 21 2.5 ltc1760 smbus controller operation .......................................................................................... ................................................... 22 2.6 ltc1760 smbalert operation .................................................................................................. .................................................... 24 3 charging algorithm overview ................................................................................................... ........................................................... 24 3.1 wake-up charging initiation ................................................................................................. ........................................................... 24 3.2 wake-up charging termination ................................................................................................ ....................................................... 24 3.3 wake-up charging current and voltage limits ................................................................................. .............................................. 25 3.4 controlled charging initiation ............................................................................................. ............................................................ 25 3.5 controlled charging termination ............................................................................................ ........................................................ 25 3.6 controlled charging current and voltage programming ......................................................................... ......................................... 26 4 system power management algorithm and battery calibration ..................................................................... ..................................... 27 4.1 turning off system power .................................................................................................... ........................................................... 27 4.2 power-by algorithm when no battery is being calibrated ...................................................................... ........................................ 27 4.3 power-by algorithm when a battery is being calibrated ....................................................................... .......................................... 27 4.4 power-by reporting .......................................................................................................... .............................................................. 27 5 battery calibration (conditioning) ............................................................................................ ........................................................... 28 5.1 selecting a battery to be calibrated ........................................................................................ ......................................................... 28 5.2 initiating calibration of selected battery .................................................................................. ........................................................ 28 5.3 terminating calibration of selected battery ................................................................................. .................................................... 28 6 mode pin operation ............................................................................................................ ................................................................ 28 6.1 stand alone charge indication ............................................................................................... .......................................................... 28 6.2 hardware charge inhibit ..................................................................................................... ............................................................. 29 6.3 charging when scl and sda are low ........................................................................................... ................................................. 29 6.4 charging with an smbus host ................................................................................................. ....................................................... 29 7 battery charger controller .................................................................................................... ............................................................... 29 7.1 charge mux switches ......................................................................................................... ............................................................ 30 7.2 dual charging ............................................................................................................... ................................................................... 30 8 powerpath controller .......................................................................................................... ................................................................ 30 8.1 autonomous powerpath switching .............................................................................................. ................................................... 31 8.2 short-circuit protection .................................................................................................... ............................................................... 31 8.3 emergency turn-off .......................................................................................................... .............................................................. 31 8.4 power-up strategy ........................................................................................................... ............................................................... 31 9 the voltage dac block ......................................................................................................... ............................................................... 31 10 the current dac block ........................................................................................................ ................................................................ 32
ltc1760 13 sn1760 1760is 1 overview the ltc1760 is composed of an smbus interface with dual port capability, a sequencer for managing system power and the charging and discharging of two batteries, a battery charger controller, charge mux controller, power- path controller, a 10-bit current dac (i dac ) and 11-bit voltage dac (v dac ). when coupled with optional system software for generating composite battery information, it forms a complete smart battery system manager for charging and selecting two smart batteries. the battery charger is controlled by the sequencer which uses the level 3 smbus interface to read chargingvoltage(), volt- age(), chargingcurrent(), current(), alarm() and batterymode(). this information, together with thermistor measurements allows the sequencer to select the charg- ing battery and safely servo on voltage and current. charging can be accomplished only if the voltage at dcdiv indicates that sufficient voltage is available from the input power source, usually an ac adapter. the charge mux, which selects the battery to be charged, is capable of charging both batteries simultaneously. the charge mux switch drivers are configured to allow charger current to share between the two batteries and to prevent current from flowing in a reverse direction in the switch. the amount of current that each battery receives will depend upon the relative capacity of each battery and the battery voltage. this can result in significantly shorter charging times (up to 50% for li-ion batteries) than sequential charging of each battery. the sequencer also selects which of the pairs of pfet switches will provide power to the system load. if the system voltage drops below the threshold set by the lopwr resistor divider, then all of the output-side pfets are turned on quickly. the input-side pfets act as diodes in this mode and power is taken from the highest voltage source available at the dcin, bat1, or bat2 inputs. the input-side powerpath switch driver that is delivering power then closes its input switch to reduce the power dissipa- tion in the pfet bulk diode. in effect, this system provides diode-like behavior from the fet switches, without the attendant high power dissipation from diodes. the host is informed of this 3-diode mode status when it polls the powerpath status register via the smbus interface. high speed powerpath switching at the lopwr trip point is handled autonomously. simultaneous discharge of both batteries is supported. the switch drivers prevent reverse current flow in the switches and automatically discharge both batteries into the load, sharing current according to the relative capacity of the batteries. simultaneous dual discharge can increase battery operating time by up to 10% by reducing losses in the switches and reducing internal battery losses associ- ated with high discharge rates. 2 the smbus interface 2.1 smbus interface overview the smbus interface allows the ltc1760 to communicate with two batteries and the smbus host. the smbus interface supports true dual port operation by allowing the smbus host to be connected to the smbus of either battery. the ltc1760 is able to operate as an smbus master or slave device. references: smart battery system manager specification: revision 1.1, sbs implementers forum. smart battery data specification: revision 1.1, sbs implementers forum. smart battery charger specification: revision 1.1, sbs implementers forum system management bus specification: revision 1.1, sbs implementers forum i 2 c-bus and how to use it: v1.0, philips semiconductor. operatio u (refer to block diagram and typical application figure)
ltc1760 14 sn1760 1760is 2.2 data bit definition of supported smbus functions. ltc1760 smbus smbus command data function mode access address code type d15 d14 d13 d12 d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 batterysystemstate() slave read/ 7'b0001_010 8'h01 status/ write control 0 0 0/1 0/1 0 0 0/1 0/1 0 0 0/1 0/1 0 0 0/1 0/1 batterysystemstatecont() slave read/ 7'b0001_010 8'h02 status/ write control 0000000/10/100/10/10/10/110/10/1 batterysysteminfo() slave read 7'b0001_010 8'h04 status battery reserved reserved system battery revision supported 0000000010000011 ltc() slave read/ 7'b0001_010 8'h3c status/ write control 0/100000010/10000001 batterymode() master read 7'b0001_011 8'h03 status 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 operatio u smb_bat4 smb_bat3 smb_bat2 smb_bat1 power_by_bat4 power_by_bat3 power_by_bat2 power_by_bat1 charge_bat4 charge_bat3 charge_bat2 charge_bat1 present_ bat4 present_ bat3 present_ bat2 present_ bat1 reserved reserved reserved reserved calibrate_bat4 calibrate_bat3 calibrate_bat2 calibrate_bat1 reserved calibrate charger_por charging_inhibit calibrate_request calibrate_request_support power_not_good ac_present power_off reserved reserved reserved reserved reserved reserved reserved turbo reserved reserved reserved ltc_version3 ltc_version2 ltc_version1 ltc_version0 reserved reserved reserved reserved reserved reserved reserved reserved condition_flag reserved reserved reserved reserved reserved reserved reserved data bit or nibble definition/allowed values (see section 2.3 for details)
ltc1760 15 sn1760 1760is ltc1760 smbus command data function mode access address code type d15 d14 d13 d12 d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 current() master read 7'b0001_011 8'h0a value 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 voltage() master read 7'b0001_011 8'h09 value 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 chargingcurrent() master read 7'b0001_011 8'h14 value 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 chargingvoltage() master read 7'b0001_011 8'h15 value 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 alarmwarning () master 7'b0001_011 8'h16 status read 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 alertresponse () slave read 7'b0001_100 n/a register see (1) byte 00010100 (1) read-byte format. 'h14 is returned as the interrupt address of the ltc1760. data bit or nibble definition/allowed values (see section 2.3 for details) va15 va14 va13 va12 va11 va10 va09 va08 va07 va06 va05 va04 va03 va02 va01 va00 ir15 ir14 ir13 ir12 ir11 ir10 ir09 ir08 ir07 ir06 ir05 ir04 ir03 ir02 ir01 ir00 vr15 vr14 vr13 vr12 vr11 vr10 vr09 vr08 vr07 vr06 vr05 vr04 vr03 vr02 vr01 vr00 over_charged terminate_charge_alarm terminate_charge_reserved over_temp_alarm terminate_discharge_alarm reserved reserved reserved reserved reserved reserved fully_discharged reserved reserved reserved reserved ara_add07 ara_add06 ara_add05 ara_add04 ara_add03 ara_add02 ara_add01 ara_add00 operatio u ia15 ia14 ia13 ia12 ia11 ia10 ia09 ia08 ia07 ia06 ia05 ia04 ia03 ia02 ia01 ia00
ltc1760 16 sn1760 1760is 2.3 description of supported smbus functions the functions are described as follows: function name() (command code) description: a brief description of the function. purpose: the purpose of the function, and an example where appropriate. smbus protocol: refer to section 2.5 and to the smbus specification for more details. input, output or input/output: a description of the data supplied to, or returned by, the function. whenever the ltc1760 encounters a valid command with invalid data, it acks the command, and ignores the invalid data. for example, if an attempt is made to select battery a and b to simultaneously communicate with the system host, the ltc1760 will just ignore the request. 2.3.1 batterysystemstate() ('h01) description: this function returns the present state of the ltc1760 and allows access to individual batteries. the information is broken into four nibbles that report: which battery is communicating with the smbus host which battery(s), if any, or ac is powering the system which battery(s) is connected to the smart charger which battery(s) is present. the ltc1760 provides a mechanism to notify the system whenever there is a change in its state. specifically, the ltc1760 provides the system with a notification when- ever: ? a battery is added or removed (polling or smbalert). ? ac power is connected or disconnected (polling or smbalert). ? the ltc1760 autonomously changes the configura tion of the battery(s) supplying power (polling only). ? the ltc1760 autonomously changes the configura tion of the battery(s) being charged (polling only). purpose: used by the smbus host to determine the present state of the ltc1760 and the attached batteries. it also may be used to determine the state of the battery system after the ltc1760 notifies the smbus host of a change via smbalert. smbus protocol: read or write word. input/output: word - refer to section 2.2 for bit map- ping. smb_bat[4:1] the read/write smb_bat[4:1] nibble is used by the smbus host to select with which individual battery to communi- cate or to determine with which individual battery it is communicating. for example, an application that displays the remaining capacity of all batteries would write to this nibble to individually select each battery in turn and get its capacity. allowed values are: 'b0010: smbus host is communicating with battery 2. 'b0001: smbus host is communicating with battery 1. (power on reset value) to change this nibble, set only one of the lower two bits of this nibble high. all other values will simply be ignored. power_by_bat[4:1] the read only power_by_bat[4:1] nibble is used by the smbus host to determine which battery(s) is powering the system. all writes to this nibble will be ignored. allowed values are: 'b0011: system being powered by battery 2 and battery 1 simultaneously. 'b0010: system being powered by battery 2. 'b0001: system being powered by battery 1. 'b0000: system being powered by ac. operatio u
ltc1760 17 sn1760 1760is charge_bat[4:1] the read only charge_bat[4:1] nibble is used by the smbus host to determine which, if any, battery is being charged. all writes to this nibble will be ignored. allowed values are: 'b0011: battery 2 and battery 1 being charged. 'b0010: battery 2 is being charged. 'b0001: battery 1 is being charged. 'b0000: no battery being charged. an indication that multiple batteries are being charged simultaneously does not indicate that the batteries are being charged at the same rate or that they will complete their charge at the same time. to actually determine when an individual battery will be fully charged, use the smb_bat[4:1] nibble to individually select the battery of interest and read the timetofull() value. present_bat[4:1] the read only present_bat[4:1] nibble is used by the smbus host to determine how many and which batteries are present. all writes to this nibble will be ignored. allowed values are: 'b0011: battery 2 and battery 1 are present. 'b0010: battery 2 is present. 'b0001: battery 1 is present. 'b0000: no batteries are present. 2.3.2 batterysystemstatecont() ('h02) description: this function returns additional state information of the ltc1760 and provides an interface to prohibit charging. this command also removes any requirement for the smbus host to communicate directly with the charger to obtain ac presence information. when the ltc1760 is used, access to the charger address, 'h12, is blocked. purpose: used by the smbus host to retrieve additional state information from the ltc1760 and the overall system power configuration. it may also be used by the system to prohibit any battery charging. smbus protocol: read or write word. input/output: word - refer to section 2.2 for bit map- ping ac_present bit the read only ac_present bit is used to show the user the status of ac availability to power the system. it may be used internally by the smbus host in conjunction with other information to determine when it is appropriate to allow a battery conditioning cycle. whenever there is a change in the ac status, the ltc1760 asserts smbalert low. in response, the system has to read this register to determine the actual presence of ac. the ltc1760 uses the dcdiv pin to measure the presence of ac. allowed values are: 'b1: the ltc1760 has determined that ac is present. 'b0: the ltc1760 has determined that ac is not present. power_not_good bit the read only power_not_good bit is used to show that the voltage delivered to the system load is inadequate. this is determined by the comparator on the lopwr pin. allowed values are: 'b1: the ltc1760 has determined that the voltage delivered to the system load is inadequate. 'b0: the ltc1760 has determined that the voltage delivered to the system load is adequate. calibrate_request_support bit the read only calibrate_request_support bit is always set to indicate that the ltc1760 has a mechanism to determine when any of the attached batteries are in need of a calibration cycle. operatio u
ltc1760 18 sn1760 1760is operatio u calibrate_request bit the read only calibrate_request bit is set whenever the ltc1760 has determined that one or more of the connected batteries need a calibration cycle. allowed values are: 'b1: the ltc1760 has determined that one or both batteries requires calibration. 'b0: the ltc1760 has determined that no batteries require calibration. charging_inhibit bit the read/write charging_inhibit is used by the smbus host to inhibit charging or to determine if charging is inhibited. this bit is also set if mode is used to inhibit charging. allowed values are: 'b1: the ltc1760 must not allow any battery charging to occur. 'b0: the ltc1760 may charge batteries as needed, (power on reset value). charger_por bit the read/write charger_por bit is used to force a charger power on reset. writing a 1 to this bit will cause a charger power on reset with the following effects. ? charging will be turned off and wake-up charging will be resumed. this is the same as if the batteries were removed and then reinserted. ? the three minute wake-up watchdog timer will be restarted. writing a 0 to this bit has no effect. a read of this bit always returns a 0. calibrate bit the read/write calibrate bit is used either to show the status of battery calibration cycles in the ltc1760 or to begin or end a calibration cycle. calibrate_bat[4:1] nibble the read/write calibrate_bat[4:1] nibble is used by the smbus host to select the battery to be calibrated or to determine which individual battery is being calibrated. allowed read values are: 'b0010: battery 2 is being calibrated . calibrate must be 1. 'b0001: battery 1 is being calibrated. calibrate must be 1. 'b0000: no batteries are being calibrated. allowed write values are: 'b0010: select battery 2 for calibration. 'b0001: select battery 1 for calibration. 'b0000: allow ltc1760 to choose battery to be calibrated. all other values will simply be ignored. this provides a mechanism to update the other batterysystemstatecont() bits without altering this nibble. 2.3.3 batterysysteminfo ()('h04) description: the smbus host uses this command to determine the capabilities of the ltc1760. purpose: allows the smbus host to determine the number of batteries the ltc1760 supports as well as the specifica- tion revision implemented by the ltc1760. smbus protocol: read word input/output: word refer to section 2.2 for bit mapping. batteries_supported nibble the read only batteries_supported nibble is used by the smbus host to determine how many batteries the ltc1760 can support. the two-battery ltc1760 always returns 'b0011 for this nibble.
ltc1760 19 sn1760 1760is battery_system_revision nibble the read only battery_system_revision nibble re- ports the version of the smart battery system manager specification supported. ltc1760 returns 'b1000 for this nibble, indicating version 1.0 without optional pec support. 2.3.4 ltc() ('h3c) description: this function returns the ltc version nibble and allows the user to perform expanded smart battery system manager functions. purpose: used by the smbus host to determine the version of the ltc1760 and to program and monitor turbo and power_off special functions. smbus protocol: read or write word. input/output: word refer to section 2.2 for bit mapping. power_off bit this read/write bit allows the ltc1760 to turn off all power path sources. allowed values: 'b1: all power path sources are off. 'b0: all power path sources are enabled. (power on reset value). turbo bit this read/write bit allows the ltc1760 to enter turbo charging mode. allowed values: 'b1: turbo charging mode enabled. 'b0: turbo charging mode disabled. (power on reset value). ltc_version[3:0] nibble this read only nibble always returns 'b0001 as the ltc1760 version. 2.3.5 batterymode() ('h03) description: this function is used by the ltc1760 to read the battery mode register. purpose: allows the ltc1760 to determine if a battery requires a conditioning/calibration cycle. smbus protocol: read word. ltc1760 reads battery 1 or battery 2 as an smbus master. input/output: word refer to section 2.2 for bit mapping. condition_flag bit the condition_flag bit is set whenever the battery requires calibration. allowed values: 'b1 - battery requires calibration. (also known as a condition cycle request). 'b0 - battery does not require calibration. 2.3.6 voltage() ('h09) description: this function is used by the ltc1760 to read the actual cell-pack voltage . purpose: allows the ltc1760 to determine the cell pack voltage and close the charging voltage servo loop. smbus protocol: read word. ltc1760 reads battery 1 or battery 2 as an smbus master. output: unsigned integer battery terminal voltage in milli-volts. refer to "section 2.2" for bit mapping. units: mv. range: 0 to 65,535 mv. operatio u
ltc1760 20 sn1760 1760is 2.3.7 current() ('h0a) description: this function is used by the ltc1760 to read the actual current being supplied through the battery terminals. purpose: allows the ltc1760 to determine how much current a battery is receiving through its terminals and close the charging current servo loop. smbus protocol: read word. ltc1760 reads battery 1 or battery 2 as an smbus master. output: signed integer (2s complement) charge/dis- charge rate in ma increments - positive for charge, nega- tive for discharge. refer to "section 2.2" for bit mapping. units: ma. range: 0 to 32,767 ma for charge or 0 to -32,768 ma for discharge. 2.3.8 chargingcurrent() ('h14) description: this function is used by the ltc1760 to read the smart batterys desired charging current. purpose: allows the ltc1760 to determine the maximum charging current. smbus protocol: read word. ltc1760 reads battery 1 or battery 2 as an smbus master. output: unsigned integer maximum charger output current in ma. refer to "section 2.2" for bit mapping. units: ma. range: 0 to 65,534 ma. 2.3.9 chargingvoltage() ('h15) description: this function is used by the ltc1760 to read the smart batterys desired charging voltage. purpose: allows the ltc1760 to determine the maximum charging voltage. smbus protocol: read word. ltc1760 reads battery 1 or battery 2 as an smbus master. output: unsigned integer charger output voltage in mv. refer to "section 2.2" for bit mapping. units: mv. range: 0 to 65,534 mv. 2.3.10 alarmwarning () ('h16) description: this function is used by the ltc1760 to read the smart battery alarm register. purpose: allows the ltc1760 to determine the state of all applicable alarm flags. smbus protocol: read word. ltc1760 reads battery 1 or battery 2 as an smbus master. output: unsigned integer - refer to section 2.2 for bit mapping. over_charged_alarm bit the read only over_charged_alarm bit is used by the ltc1760 to determine if charging may continue. allowed values are: 'b1: the ltc1760 will not charge this battery. 'b0: the ltc1760 may charge this battery if other conditions permit charging. terminate_charge_alarm bit the read only terminate_charge_alarm bit is used by the ltc1760 to determine if charging may continue. allowed values are: 'b1: the ltc1760 will not charge this battery. 'b0: the ltc1760 may charge this battery if other conditions permit charging. operatio u
ltc1760 21 sn1760 1760is terminate_charge_reserved bit the read only terminate_charge_reserved bit is used by the ltc1760 to determine if charging may con- tinue. allowed values are: 'b1: the ltc1760 will not charge this battery. 'b0: the ltc1760 may charge this battery if other conditions permit charging. over_temp_alarm bit the read only over_temp_alarm is used by the ltc1760 to determine if charging may continue. allowed values are: 'b1: the ltc1760 will not charge this battery. 'b0: the ltc1760 may charge this battery if other conditions permit charging. terminate_discharge_alarm bit the read only terminate_discharge_alarm bit is used by the ltc1760 to determine if discharge from the battery is still allowed. this is used for power path man- agement and battery calibration. allowed values are: 'b1: the ltc1760 will terminate calibration and should try to not use this battery in the power path. when all other power paths fail the ltc1760 will ignore this alarm and still try to supply system power from this source. 'b0: the ltc1760 may continue discharging this battery. fully_discharged bit the read only fully_discharged bit is used by the ltc1760 to determine if discharge from the battery is still allowed. this is used for power path management and battery calibration. allowed values are: 'b1: the ltc1760 will terminate calibration and should try to not use this battery in the power path. when all other power paths fail the ltc1760 will ignore this alarm and still try to supply system power from this source. operatio u 'b0: the ltc1760 may continue discharging this battery. 2.3.11 alertresponse () description: the smbus host uses the alert response address (ara) to quickly identify the generator of an smbalert# event. purpose: the ltc1760 will respond to an ara if the smbalert signal is actively pulling down the smbalert# bus. the ltc1760 will follow the prioritization reporting as defined in the system management bus specification. smbus protocol: a 7-bit addressable device responds to an ara. output: the device address will be sent to the smbus host. the ltc1760 device address is 0x14 (or 0x0a if just looking at the 7 bit address field). the following events will cause the ltc1760 to pull-down the smbalert# bus through the smbalert pin: ? change of ac_present in the batterysystemstatecont() function. ? change of battery_present in the batterysystemstate() function. ? internal power on reset condition. refer to "section 2.2" for bit mapping. 2.4 smbus dual port operation the smbus interface includes the ltc1760s smbus controller, as well as circuitry to arbitrate and connect the battery and smbus host interfaces. the smbus controller generates and interprets all ltc1760 smbus functions. the dual port operation allows the smbus host to be connected to the smbus of either battery by setting the smb_bat[4:1] nibble. arbitration is handled by stretch- ing an smbus start sequence when a bus collision might occur. whenever configurations are switched, the ltc1760 will generate a harmless smbus reset on smb1 and smb2 as required. the four possible configurations are illus- trated in figure 1. sample smbus communications are shown in figures 2 and 3.
ltc1760 22 sn1760 1760is 2.5 ltc1760 smbus controller operation smbus communication with the ltc1760 is handled by the smbus controller, a sub-block of the smbus interface. data is clocked into the smbus controller block shift register after the rising scl edge. data is clocked out of the smbus control block shift register after the falling edge of scl. the ltc1760 acting as a slave will acknowledge (ack) each byte of serial data. the command byte will be nacked if an invalid command code is transmitted to the ltc1760. the smbus controller must respond if ad- dressed as a combined smart battery system manager (address 14). a valid address includes a legal read/write bit. the smbus controller will ignore invalid data although host ltc1760 smbus controller smb* smb1* smb2* bat2 bat1 host, ltc1760 and bat1 can communicate. bat2 originated commands are ignored. host ltc1760 smbus controller smb* smb1* smb2* bat2 bat1 ltc1760 and bat2 can communicate. host and bat1 originated commands are stretched if the ltc1760 is communicating with bat2. ltc1760 and bat1 can communicate. host and bat2 originated commands are stretched if the ltc1760 is communicating with bat1. host ltc1760 smbus controller smb* smb1* smb2* bat2 bat1 host, ltc1760 and bat2 can communicate. bat1 originated commands are ignored. host ltc1760 smbus controller smb* smb1* smb2* bat2 bat1 (b) (a) (d) (c) 1760 f01 *smb includes scl and sda, smb1 includes scl1 and sda1, and smb2 includes scl2 and sda2. figure 1. switch configurations used by the ltc1760 for managing dual port battery communication. the data transmission with the invalid data will still be acked. when the ltc1760, acting as a bus master receives a nack, it will terminate the transmission and provide a stop condition on the bus. detection of a stop condition, power on reset, or smbus time-out will reset the controller to an initial state at any time. the ltc1760 supports ara, word write and word read protocols as an smbus slave. the ltc1760 supports word read protocol as an smbus master. refer to system management bus specification for complete description of required operation and symbols. operatio u
ltc1760 23 sn1760 1760is figure 3. ltc1760 queries battery 1 followed by battery 2 for requested current. (configuration b) smbus dual port scl sda scl1 sda1 scl2 sda2 smbus dual port scl sda scl1 sda1 scl2 sda2 figure 2. ltc1760 stretches host? communication with battery 1 while it completes a read of battery 2. (configuration b) operatio u
ltc1760 24 sn1760 1760is 2.6 ltc1760 smbalert operation the smbalert pin allows the ltc1760 to signal to the smbus host that there has been a change of status. this pin is asserted low whenever there is a change in battery presence, ac presence or after a power on reset event. this pin is cleared during an alert response or any of the following reads: batterysystemstate(),batterysystemstatecont(), batterysysteminfo(), or ltc(). 3 charging algorithm overview 3.1 wake-up charging initiation the following conditions must be met in order to allow wake-up charging: 1. the battery thermistor must be cold-range, ideal- range, or under-range. 2. ac must be present. 3. batterysystemstatecont(charging_inhibit) must be de-asserted (or low). 4. hardware controlled charging inhibit must be de-asserted (mode not low with v dds high) wake-up charging initiates when a newly inserted battery does not respond to any ltc1760 master read com- mands. only one battery will wake-up charge at a time. when two batteries are inserted and both require wake-up charging, battery 1 will wake-up charge first. battery 2 will only wake-up charge when battery 1 terminates wake-up charging. wake-up charging takes priority over controlled charging; this prevents one battery from tying up the charger when it would be advantageous to dual charge two deeply discharged batteries. the ltc1760 will attempt to reinitiate wake-up charging on both batteries after the smbus host asserts batterysystemstatecont(charger_por) or a power on reset event. this will reset any wake-up charging safety timers and is equivalent to removing and reinserting both batteries. the ltc1760 will attempt to reinitiate wake-up charging on a battery if the battery is not being charged and fails to respond to an smbus query. this is an important feature for handling deeply discharged nimh batteries. these batteries may begin to talk while being charged and go silent once charging has stopped. wake-up charging is disabled if the battery thermistor is cold-range or under-range and the battery has been charged for longer than t timeout . 3.2 wake-up charging termination the ltc1760 will terminate wake-up charging when any of the following conditions are met: 1. battery removal (thermistor indicating over-range) 2. ac is removed. 3. the smbus host issues a calibration request by setting batterysystemstatecont(calibrate) high. 4. any response to an ltc1760 master read of chargingcurrent(), current(), chargingvoltage(), or volt- age(). note that the ltc1760 ignores all writes from the battery. 5. any of the following alarmwarning() bits asserted high: over_charged_alarm terminate_charge_alarm terminate_charge_reserved over_temp_alarm note that the ltc1760 ignores all writes from the battery. each batterys charge alarm is cached inside the ltc1760. this bit will be set when any of the upper four bits of the batterys alarmwarning() response are set. this bit will remain set if a subsequent alarmwarning() fails to re- spond. the cached alarm will be cleared by any of the following conditions. a) associated battery is removed. b) a subsequent alarmwarning() clears all charge alarm bits for the associated battery. c) a power on reset event. d) the smbus host asserts batterysystemstatecont(charger_por) high. 6. an smbus host write asserts the ltc1760 batterysystemstatecont(charging_inhibit) high. operatio u
ltc1760 25 sn1760 1760is 7. hardware controlled charging inhibit is asserted (mode low with v dds high). 8. the thermistor of the battery being charged indicates cold-range and the battery has been charged for longer than t timeout . 9. the thermistor of the battery being charged indicates under-range and the battery has been charged for longer than t timeout . 10. the thermistor of the battery being charged indicates hot-range. 11. any smbus communication line is grounded for longer than t query. 12. batterysystemstatecont(power_not_good) is high. 13. the emergency off feature has been asserted using the dcdiv input pin. 3.3 wake-up charging current and voltage limits the wake-up charging current is fixed at i wake-up for all values of i limit . wake-up charging uses the low current mode described in section 10. the wake-up charging voltage is not limited by the v limit function. 3.4 controlled charging initiation all of the following conditions must be met in order to allow controlled charging of a given battery. one or both batteries may be control charged at a time. 1. the battery thermistor must be cold-range, ideal- range, or under-range. 2. ac must be present. 3. batterysystemstatecont(charging_inhibit) must be de-asserted (or low). 4. hardware controlled charging inhibit must be de-asserted (mode not low with v dds high). 5. the battery responds to an ltc1760 master read of alarm() with all charge alarms deasserted. 6. the battery responds to an ltc1760 master read of chargingvoltage() with a non zero voltage request value. 7. the battery responds to an ltc1760 master read of voltage(). 8. the battery responds to an ltc1760 master read of chargingcurrent() with a non zero current request value. 9. the battery responds to an ltc1760 master read of current(). the following charging related functions are polled each t query : alarm(), chargingvoltage(), voltage(), chargingcurrent(), and current(). 3.5 controlled charging termination ltc1760 will terminate controlled charging when any of the following conditions are met: 1. battery removal, or thermistor indicating over-range. 2. ac removal. 3. the smbus host issues a calibration request by setting batterysystemstatecont(calibrate) high. 4. an ltc1760 master read of chargingcurrent() return- ing a zero current request. 5. an ltc1760 master read of chargingvoltage() return- ing a zero voltage request. 6. any of the following alarmwarning() bits asserted high: over_charged_alarm terminate_charge_alarm terminate_charge_reserved over_temp_alarm note that the ltc1760 ignores all writes from the battery. each batterys charge alarm is cached inside the ltc1760. this bit will be set when any of the upper four bits of the batterys alarmwarning() response are set. operatio u
ltc1760 26 sn1760 1760is this bit will remain set if a subsequent alarmwarning() fails to respond. the cached alarm will be cleared by any of the following conditions. a) associated battery is removed. b) a subsequent alarmwarning() clears all charge alarm bits for the associated battery. c) a power on reset event. d) the smbus host asserts batterysystemstatecont(charger_por) high. 7. an smbus host write asserts the ltc1760 batterysystemstatecont(charging_inhibit) high. 8. hardware controlled charging inhibit is asserted (mode low with v dds high). 9. the smbus of the battery being charged has stopped acknowledging smbus read commands for longer than t timeout. 10. the thermistor of the battery being charged indicates hot-range. 11. any smbus communication line is grounded for longer than t query . 12. batterysystemstatecont(power_not_good) is high. 13. the emergency off feature has been asserted using the dcdiv input pin. whenever changing conditions cause either battery to stop charging, charging is stopped immediately for all batteries and the voltage and current algorithms are reset to zero. charging is not resumed until all the conditions for controlled charging are met. 3.6 controlled charging current and voltage programming the ltc1760 monitors the requested and actual current in each battery and increases the programmed current un- less one of the following conditions is met: a) the actual current exceeds the requested current in either battery. b) the total programmed current equals the maximum of the two requested currents + i limit /32 and ltc(turbo) is de-asserted (or low). c) only one battery is charging and the programmed current equals the requested current + i limit /32. d) the total programmed current equals i limit . the programmed current is updated every t query . it is changed by the difference between the actual and re- quested currents. ltc(turbo) provides a mechanism for the smbus host to put additional current into both batteries. normally the ltc1760 will limit the current into both batteries to the maximum of the two requested currents + i limit /32. when ltc(turbo) is asserted, this restriction is removed, allowing the charger to output as much as i limit into both batteries. whenever changing conditions cause either battery to stop charging, the current algorithm is reset to zero. the ltc1760 monitors the requested and actual voltages in each battery and increases the programmed voltage by 16mv each t query unless one of the following conditions are met: a) the actual voltage exceeds the requested voltage in either battery. b) the actual voltage exceeds v limit . this is an extremely important feature of the ltc1760 since it allows the charger to servo on the internal cell voltage of the battery as determined by the smart battery. this voltage may be significantly lower than the battery pack terminal voltage which is used by all level 2 chargers. the advantage for the ltc1760 is improved charge time, safety, and a more completely charged battery. the voltage correction cannot exceed the minimum re- quested voltage by more than 512mv. when decrementing, the programmed voltage is reduced by 16mv each t query . whenever changing conditions cause either battery to stop charging, the voltage algorithm is reset to zero. operatio u
ltc1760 27 sn1760 1760is 4 system power management algorithm and battery calibration 4.1 turning off system power the ltc1760 allows the user to turn off system power using the ltc(power_off) bit. when power_off is asserted high all power management functions are by- passed and the ltc1760 will turn off dcin, bat2 and bat1 power paths. this feature allows the user to power down the system. charging is still allowed when power_off is asserted high. 4.2 power-by algorithm when no battery is being calibrated the ltc1760 will always attempt to maintain system power. the preferred configuration is to remain in 3- diode mode. in 3-diode mode, power will be provided by bat1, bat2 and dcin with the source at the highest voltage potential automatically providing all the power. sources at similar voltage potentials will share power based on their capacity. the following conditions will cause the ltc1760 to modify its preferred power-by algorithm. 1. a battery issues a terminate discharge alarm and ac_present is high. the ltc1760 will select the other battery and dcin to power the system. 2. a battery issues a terminate discharge alarm and ac_present is low. the ltc1760 will select the other battery to power the system. 3. a battery issues a terminate discharge alarm, ac_present is low, and the other battery is not present or has previously alarmed. the ltc1760 will autono- mously try to restore power by entering 3-diode mode. the 3-diode mode will ignore terminate_discharge and fully_discharged alarms. 4.3 power-by algorithm when a battery is being calibrated during battery calibration, the battery being calibrated is the only device powering the system. this will be reflected in the reported power_by[4:1] bits. see section 5 for more information on battery calibration. 4.4 power-by reporting the following tables illustrate how batterysystem state(power_by_bat[4:1]) interprets power path conditions. operatio u power reporting for batteries being calibrated ac_present calibrate_bat2 calibrate_bat2 power_by_bat[4:1] 1 0 0 'b0000 1 0 1 'b0001 1 1 0 'b0010 *states not shown are not allowed ac_present present_bat2 present_bat1 power_by_bat[4:1] 0 0 0 'b0000 0 0 1 'b0001 0 1 0 'b0010 0 1 1 'b0011 1 0 0 'b0000 1 0 1 'b0000 1 1 0 'b0000 1 1 1 'b0000 power reporting with ac_present low and both batteries present, as a function of power alarms. battery 2 battery 1 power alarm power alarm ac_present (note 1) (note 1) power_by_bat[4:1] 0 0 0 'b0011 0 0 1 'b0010 0 1 0 'b0001 0 1 1 'b0011 1 x x 'b0000 note 1: a power alarm means that alarm() has returned terminate_discharge=1 or fully_discharged_alarm=1 power reporting when batterysystemstatecont(power_not_good) is high and the ltc1760 has autonomously entered 3-diode mode power reporting as a function of battery presence ac_present present_bat2 present_bat1 power_by_bat[4:1] 1 x x 'b0000 0 0 0 'b0000 0 0 1 'b0001 0 1 0 'b0010 0 1 1 'b0011
ltc1760 28 sn1760 1760is 5 battery calibration (conditioning) calibration allows the smbus host to fully discharge a battery for conditioning purposes. the smbus host may determine the battery to be discharged or allow the ltc1760 to choose based on the batteries request to be condi- tioned. 5.1 selecting a battery to be calibrated option 1) smbus host chooses battery to be calibrated using batterysystemstatecont(calibrate_bat[4:1]) allowed values: 'b0001: set calibrate_bat1. only has an effect if battery 1 batterymode(condition_flag) is high . may not be updated if a calibration is in progress. 'b0010: set calibrate_bat2. only has an effect if battery 2 batterymode(condition_flag) is high . may not be updated if a calibration is in progress. 'b0000: clears calibrate_bat1 and calibrate_bat2 and allows ltc1760 to chose. power on reset default. may not be updated if a calibration is in progress. option 2) smbus host allows ltc1760 to choose battery to be calibrated. batterysystemstatecont(calibrate_bat[4:1]) =`b0000. see previous option. the ltc1760 determines that the battery requires calibra- tion by reading batterymode(condition_flag). this flag is cached in the ltc1760. the ltc1760 sets batterysystemstatecont(calibrate_request) high. the ltc1760 will always select the battery that is request- ing calibration. if both batteries are requesting calibration, the ltc1760 will select battery 1. if neither battery is requesting calibration, then calibration cannot occur. 5.2 initiating calibration of selected battery the smbus host initiates a calibration by writing to batterysystemstatecont(calibrate). follow rules of the previous section to preserve battery intended for calibra- tion. the smbus host must only set the calibration bit once per calibration. operatio u the ltc1760 will discharge the selected battery as long as the calibration is in progress (calibrate high). updates to the cached batterymode(condition_flag) will be inhibited while calibrate is asserted. this means that discharge of the battery will continue even if the battery clears the condition_flag. 5.3 terminating calibration of selected battery calibration will end when calibrate is cleared. cali- brate will be cleared when: ? ac is removed. ? the battery being calibrated is removed. when the battery being calibrated is removed, the ltc1760 will automatically calibrate the other battery if it is requesting calibration. ? batterysystemstatecont(power_not_good) is high. ? the battery sets alarm warning (terminate_discharge) high. ? the battery sets alarm warning (fully_discharged) high. ? a zero is written to the calibrate bit. the ltc1760 will attempt to initiate a charge cycle after the discharge cycle is completed. 6 mode pin operation the mode pin is a multifunction pin that allows the ltc1760 to: 1) display charging status in stand alone operation; 2) activate hardware charge inhibit and; 3) charge when scl and sda are low; 4) charge with an smbus host. 6.1 stand alone charge indication when mode is tied to gnd and v vdds < v il_vdds , the function of sda, smbalert, and scl are changed as described below. sda is an output and is used to monitor charging status of battery 2. allowed valued are: low: battery 2 is charging.
ltc1760 29 sn1760 1760is high: battery 2 not charging (ac is not present or battery is not present). blinking: battery 2 charge complete (ac is present, battery is present and not charging). smbalert is used to monitor charging status of battery1. allowed valued are: low: battery 1 is charging. high: battery 1 not charging (ac is not present or battery is not present). blinking: battery 1 charge complete (ac is present, battery is present and not charging). scl is an input and is used to determine the blinking rate of sda and smbalert. tie scl high if blinking is not desired. this will provide two different states to indicate charging (output low) and not charging (output high). 6.2 hardware charge inhibit when mode is tied to gnd and v vdds >v ih_vdds ,charging is inhibited and batterysystemstatecont(charging_inhibit) will report a logic high. 6.3 charging when scl and sda are low when mode is tied to v cc2 and v dds < v il_vdds , sda and scl are not used and will not interfere with ltc1760 battery communication. this feature allows the ltc1760 to autonomously charge when scl and sda are not available. this scenario might occur when smbus host has powered down and is no longer pulling up on scl and sda. 6.4 charging with an smbus host when mode is tied to v cc2 and v vdds > v il_vdds , sda and scl are used to communicate with the smbus host. 7 battery charger controller the ltc1760 charger controller uses a constant off-time, current mode step-down architecture. during normal op- eration, the top mosfet is turned on each cycle when the oscillator sets the sr latch and turned off when the main current comparator i cmp resets the sr latch. while the top mosfet is off, the bottom mosfet is turned on until either the inductor current trips the current comparator i rev , or the beginning of the next cycle. the oscillator uses the equation. t off = (v dcin - v bat )/(v dcin ? f osc ) to set the bottom mosfet on time. the result is quasi- constant frequency operation where the converter fre- quency remains nearly constant over a wide range of output voltages. this activity is diagrammed in figure 4. operatio u tgate bgate on on off off t off trip point set by i th voltage inductor current figure 4. the peak inductor current, at which i cmp resets the sr latch, is controlled by the voltage on i th . i th is in turn controlled by several loops, depending upon the situation at hand. the average current control loop converts the voltage between csp and bat to a representative current. error amp ca2 compares this current against the desired current programmed by the i dac at the i set pin and adjusts i th for the desired voltage across r sense . the voltage at bat is divided down by an internal resistor divider set by the v dac and is used by error amp ea to decrease i th if the divider voltage is above the 0.8v reference. the amplifier cl1 monitors and limits the input current, normally from the ac adapter, to a preset level (100 mv/ r cl ). at input current limit, cl1 will decrease the i th voltage and thus reduce battery charging current. an over-voltage comparator, ov, guards against transient overshoots (>7.5%). in this case, the top mosfet is turned off until the over-voltage condition is cleared. this feature is useful for batteries which load dump them- selves by opening their protection switch to perform functions such as calibration or pulse-mode charging.
ltc1760 30 sn1760 1760is + + gb1i gb1o q8 q7 from battery 1 bat1 scp 25mv 20mv off off 1760 f06 eap cp swp to load c l r sc figure 6. powerpath driver equivalent circuit the top mosfet driver is powered from a floating boot- strap capacitor c4. this capacitor is normally recharged from v cc through an external diode when the top mosfet is turned off. as v in decreases towards the selected battery voltage, the converter will attempt to turn on the top mosfet continuously (dropout). a dropout timer detects this condition and forces the top mosfet to turn off, and the bottom mosfet on, for about 200ns at 40 m s intervals to recharge the bootstrap capacitor. 7.1 charge mux switches the equivalent circuit of a charge mux switch driver is shown in figure 5. if the charger controller is not enabled, the charge mux drivers will drive the gate and source of the series connected mosfets to a low voltage and the switch is off. when the charger controller is on, the charge mux driver will keep the mosfets off until the voltage at csn rises at least 35mv above the battery voltage. gch1 is then driven with an error amplifier eac until the voltage between bat1 and csn satisfies the error amplifier or until gch1 is clamped by the internal zener diode. the time required to close the switch could be quite long (many ms) due to the small currents output by the error amp and depending upon the size of the mosfet switch. if the voltage at csn decreases below v bat1 C 20mv a comparator cc quickly turns off the mosfets to prevent reverse current from flowing in the switches. in essence, this system performs as a low forward voltage diode. operation is identical for bat2. 7.2 dual charging note that the charge mux switch drivers will operate together to allow both batteries to be charged simulta- neously. if both charge mux switch drivers are enabled, only the battery with the lowest voltage will be charged until its voltage rises to equal the higher voltage battery. the charge current will then share between the batteries according to the capacity of each battery. when batteries are controlled charging, only batteries with voltages above v chmin are allowed to charge. when a battery is wake-up charging this restriction does not apply. 8 powerpath controller the powerpath switches are turned on and off by the power management algorithm. the external pfets are usually connected as an input switch and an output switch. the output switch pfet is connected in series with the input pfet and the positive side of the short-circuit sensing resistor, r sc . the input switch is connected in series between the power source and the output pfet. the powerpath switch driver equivalent circuit is shown in figure 6. the output pfet is driven on or off by the output side driver controlling pin gb10. the gate of the input pfet is driven by an error amplifier which monitors the voltage between the input power source (bat1 in this case) and scp. if the switch is turned off, the two outputs are driven to the higher of the two voltages present across the input/ scp terminals of the switch. when the switch is instructed operatio u + + gch1 sch1 q4 q3 to battery 1 from charger bat1 csn 35mv 20mv off dcin + 10v (charge pumped) 10k 1760 f05 eac cc figure 5.charge mux switch driver equivalent circuit
ltc1760 31 sn1760 1760is to turn on, the output side driver immediately drives the gate of the output pfet approximately 6v below the highest of the voltages present at the input/scp. when the output pfet turns on, the voltage at scp will be pulled up to a diode drop below the source voltage by the bulk diode of the input pfet. if the source voltage is more than 25mv above scp, eap will drive the gate of the input pfet low until the input pfet turns on and reduces the voltage across the input/scp to the eap set point, or until the zener clamp engages to limit the voltage applied to the input pfet. if the source voltage drops more than 20mv below scp, then comparator cp turns on swp to quickly prevent large reverse current in the switch. this operation mimics a diode with a low forward voltage drop. 8.1 autonomous powerpath switching the lopwr comparator monitors the voltage at the load through the resistor divider from pin scn. if ltc (power_off) is low and the lopwr comparator trips, then all of the switches are turned on (3-diode mode) by the autonomous powerpath controller to ensure that the system is powered from the source with the highest voltage. the autonomous powerpath controller waits approximately 1second, to allow power to stabilize, and then reverts back to the powerpath switch configuration requested by the powerpath management algorithm. a power fail counter is incremented to indicate that a failure has occurred. if the power fail counter equals a value of 3, then the the autonomous powerpath controller sets the switches to 3-diode mode and batterysystem- statecont(power_not_good) will be set, provided the lopwr comparator is still detecting a low power event. this is a three-strikes-and-youre-out process which is intended to debounce the power_not_good indicator. the power fail counter is reset when battery or ac pres- ence change. 8.2 short-circuit protection short-circuit protection operates in both a current mode and a voltage mode. if the voltage between scp and scn exceeds the short-circuit comparator threshold v tsc for more than 15ms, then all of the powerpath switches are turned off and batterysystemstate- cont (power_not_good) is set. similarly, if the voltage operatio u at scn falls below 3v for more than 15ms, then all of the powerpath switches are turned off and power_not_good is set high. the power_not_good bit is reset by removing all power sources and allowing the voltage at v plus to fall below the uvlo threshold. if the power_not_good bit is set, charging is disabled until v plus exceeds the uvlo threshold and the charger algo- rithm allows charging to resume. when a hard short-circuit occurs, it might pull all of the power sources down to near 0v potentials. the capacitors on v cc and v plus must be large enough to keep the circuit operating correctly during the 15ms short-circuit event. the charger will stop within a few microseconds, leaving a small current which must be provided by the capacitor on v plus . the recommended minimum values (1 m f on v plus and 2 m f on v cc , including tolerances) should keep the ltc1760 operating above the uvlo trip voltage long enough to perform the short-circuit function when the input voltages are greater than 8v. increasing the capaci- tor across v cc to 4.7 m f will allow operation down to the recommended 6v minimum. 8.3 emergency turn-off all of the powerpath switches can be forced off by setting the dcdiv pin to a voltage between 8v and 10v. this will have the same effect as a short-circuit event. dcdiv must be less than 5v and v plus must decrease below the uvlo threshold to re-enable the powerpath switches. the ltc1760 can recover from this condition without remov- ing power. contact applications engineering for more information. 8.4 power-up strategy. all three powerpath switches are turned on after v plus exceeds the uvlo threshold for more than 250ms. this delay is to prevent oscillation from a turn-on transient near the uvlo threshold. 9 the voltage dac block the voltage dac (vdac) is a delta-sigma modulator which controls the effective value of an internal resistor, r vset = 7.2k, used to program the maximum charger voltage. figure 7 is a simplified diagram of the vdac operation. the delta-sigma modulator and switch swv convert the vdac value to a variable resistance equal to
ltc1760 32 sn1760 1760is automatic current sharing in a dual parallel charge configuration, the ltc1760 does not actually control the current flowing into each individual battery. the capacity, or amp-hour rating, of each battery determines how the charger current is shared. this auto- matic steering of current is what allows both batteries to reach their full capacity points at the same time. in other words, given all other things equal, charge termination will happen simultaneously. a battery can be modeled as a huge capacitor and hence governed by the same laws. i = c ? (dv/dt) where: + c b1 c b2 csn 1760 f07 ea v ref v set r vset 7.2k r vf 405.3k ? s modulator swv 11 to i th dac value (11 bits) figure 7. voltage dac operation + 1760 f08 v ref i set r set 18.77k ? s modulator 10 to i th dac value (10 bits) c set (v csp ?v csn ) 3k (from ca1 amplifier) figure 8. current dac operation (11/8)r vset /(vdac (value) /2047). in regulation, v set is servo driven to the 0.8v reference voltage, v ref . r set is matched against a current derived from the voltage between pins csp and csn. this current is (v csp C v csn )/ 3k. therefore programmed current is: i chg = 0.8 v ref 3k/(r sns r set ) ? (idac (value) /1023) = (102.3mv/r sns ) ? (idac (value) /1023) operatio u applicatio s i for atio wu uu capacitors c b1 and c b2 are used to average the voltage present at the v set pin as well as provide a zero in the voltage loop to help stability and transient response time to voltage variations. 10 the current dac block the current dac is a delta-sigma modulator which controls the effective value of an internal resistor, r set = 18.77k, used to program the maximum charger current. figure 8 is a simplified diagram of the dac operation. the delta-sigma modulator and switch convert the idac value to a variable resistance equal to 1.25r set / (idac (value) /1023). in regulation, i set is servo driven to the 0.8v reference voltage, v ref , and the current from during wake-up current operation, the current dac enters a low current mode. the current dac output is pulse-width modulated with a high frequency clock having a duty cycle value of 1/8. therefore, the maximum output current provided by the charger is i max /8. the delta-sigma output gates this low duty cycle signal on and off. the delta-sigma shift registers are then clocked at a slower rate, about 40ms/bit, so that the charger has time to settle to the i max / 8 value. i = the current flowing through the capacitor c = capacity rating of battery (using amp-hour values instead of capacitance) dv = change in voltage dt = change in time the equivalent model of a set or parallel batteries is a set of parallel capacitors. since they are in parallel, the change in voltage over change in time is the same for both batteries one and two. dv/dt bat1 = dv/dt bat2
ltc1760 33 sn1760 1760is setting input current limit to set the input current limit, you need to know the minimum wall adapter current rating. subtract 5% for the input current limit tolerance and use that current to deter- mine the resistor value. r cl = 100mv/i lim i lim = adapter min current C (adapter min current ? 5%) as is often the case, the wall adapter will usually have at least a +10% current limit margin and many times one can simply set the adapter current limit value to the actual adapter rating (see table 1). table 1. common r cl resistor values adapter rcl value* rcl power rcl power rating a ( w ) 1% dissipation (w) rating (w) 1.5 0.06 0.135 0.25 1.8 0.05 0.162 0.25 2 0.045 0.18 0.25 2.3 0.039 0.206 0.25 2.5 0.036 0.225 0.5 2.7 0.033 0.241 0.5 3 0.030 0.27 0.5 *values shown above are rounded to nearest standard value. extending system to more than 2 batteries the ltc1760 can be extended to manage systems with more than 3 sources of power. contact linear technology applications engineering for more information. charge termination issues batteries with constant-current charging and voltage- based charger termination might experience problems from here we can simplify. i bat1 /c bat1 = dv/dt = i bat2 /c bat2 i bat2 = i bat1 c bat2 /c bat1 at this point you can see that the current divides as the ratio of the two batteries capacity ratings. the sum of the current into both batteries is the same as the current being supply by the charger. this is independent of the mode of the charger (cc or cv). i chrg = i bat1 + i bat2 from here we solve for the actual current for each battery. i bat2 = i chrg c bat2 /(c bat1 + c bat2 ) i bat1 = i chrg c bat1 /(c bat1 + c bat2 ) please note that the actual observed current sharing will vary from manufactures claimed capacity ratings since it is actual physical capacity rating at the time of charge. capacity rating will change with age and use and hence the current sharing ratios can change over time. adapter limiting an important feature of the ltc1760 is the ability to automatically adjust charging current to a level which avoids overloading the wall adapter. this allows the prod- uct to operate at the same time that batteries are being charged without complex load management algo rithms. additionally, batteries will automatically be charged at the maximum possible rate of which the adapter is capable. this feature is created by sensing total adapter output current and adjusting charging current downward if a preset adapter current limit is exceeded. true analog control is used, with closed loop feedback ensuring that adapter load current remains within limits. amplifier cl1 in figure 9 senses the voltage across r cl , connected between the clp and dcin pins. when this voltage ex- ceeds 100mv, the amplifier will override programmed charging current to limit adapter current to 100mv/r cl . a lowpass filter formed by 5k w and 0.1 m f is required to eliminate switching noise. if the current limit is not used, clp should be connected to dcin. figure 9. 100mv + 5k clp dcin 1760 f09 0.1 m f + r cl * c in v in cl1 ac adapter input *r cl = 100mv adapter current limit + applicatio s i for atio wu uu
ltc1760 34 sn1760 1760is with reductions of charger current caused by adapter limiting. it is recommended that input limiting feature be defeated in such cases. consult the battery manufacturer for information on how your battery terminates charging. setting charger output current limit the ltc1760 current dac and the pwm analog circuitry must coordinate the setting of the charger current. failure to do so will result in incorrect charge currents. table 2. recommended resistor values i max (a) r sense ( w ) 1% r sense (w) r ilim ( w ) 1% 1 0.100 0.25 0 2 0.05 0.25 10k 3 0.025 0.5 33k 4 0.025 0.5 open warning do not change the value of r ilim during opera- tion. the value must remain fixed and track the r sense value at all times. changing the current setting can result in currents that greatly exceed the requested value and potentially damage the battery or overload the wall adapter if no input current limiting is provided. setting charger output voltage limit the value of an external resistor connected from the v limit pin to gnd determines one of five voltage limits that are applied to the charger output value. see table 3. these limits provide a measure of safety with a hardware restric- tion on charging voltage, which cannot be overridden by software. this voltage sets the limit that will be applied to the battery as reported by battery. since the battery internal voltage monitor point is the actual cell voltage, you may see higher voltages, up to 512mv higher, at the external charger terminals due to the voltage servo loop action. see operations section 3.6 for more information on the voltage servo system. table 3. recommended resistor values for r vlim v max r vlim 1% up to 8.4v 0 w (short to ground) up to 12.6v 10k up to 16.8v 33k up to 21.0v 100k up to 32.7v (no limit) open (or short to v cc2 ) inductor selection higher operating frequencies allow the use of smaller inductor and capacitor values. a higher frequency gener- ally results in lower efficiency because of mosfet gate charge losses. in addition, the effect of inductor value on ripple current and low current operation must also be considered. the inductor ripple current d i l decreases with higher frequency and increases with higher v in . d i fl v v v l out out in = ()( ) - ? ? ? ? 1 1 accepting larger values of d i l allows the use of low inductances, but results in higher output voltage ripple and greater core losses. a reasonable starting point for setting ripple current is d i l = 0.4(i max ). in no case should d i l exceed 0.6(i max ) due to limits imposed by irev and ca1. remember the maximum d i l occurs at the maxi- mum input voltage. in practice 10 m h is the lowest value recommended for use. charger switching power mosfet and diode selection two external power mosfets must be selected for use with the ltc1760 charger: an n-channel mosfet for the top (main) switch and an n-channel mosfet for the bottom (synchronous) switch. the peak-to-peak gate drive levels are set by the v cc voltage. this voltage is typically 5.2v. consequently, logic- level threshold mosfets must be used. pay close atten- tion to the b vdss specification for the mosfets as well; many of the logic level mosfets are limited to 30v or less. selection criteria for the power mosfets include the on resistance r ds(on) , reverse transfer capacitance c rss , input voltage and maximum output current. the ltc1760 charger is always operating in continuous mode so the duty cycles for the top and bottom mosfets are given by: main switch duty cycle = v out /v in synchronous switch duty cycle = (v in C v out )/v in the mosfet power dissipations at maximum output current are given by: applicatio s i for atio wu uu
ltc1760 35 sn1760 1760is p main = v out /v in (i max ) 2 (1 + ddt )r ds(on) + k(v in ) 2 (i max )(c rss )(f) p sync = (v in C v out )/v in (i max ) 2 (1 + ddt ) r ds(on) where ddt is the temperature dependency of r ds(on) and k is a constant inversely related to the gate drive current. both mosfets have i 2 r losses while the topside n-channel equation includes an additional term for transi- tion losses, which are highest at high input voltages. for v in < 20v the high current efficiency generally improves with larger mosfets, while for v in > 20v the transition losses rapidly increase to the point that the use of a higher r ds(on) device with lower c rss actually provides higher efficiency. the synchronous mosfet losses are greatest at high input voltage or during a short-circuit when the duty cycle in this switch is nearly 100%. the term (1 + ddt ) is generally given for a mosfet in the form of a normalized r ds(on) vs temperature curve, but d = 0.005/ c can be used as an approximation for low voltage mosfets. c rss is usually specified in the mosfet characteristics. the constant k = 1.7 can be used to estimate the contribu- tions of the two terms in the main switch dissipation equation. if the ltc1760 charger is to operate in low dropout mode or with a high duty cycle greater than 85%, then the topside n-channel efficiency generally improves with a larger mosfet. using asymmetrical mosfets may achieve cost savings or efficiency gains. the schottky diode d1, shown in the typical application, conducts during the dead-time between the conduction of the two power mosfets. this prevents the body diode of the bottom mosfet from turning on and storing charge during the dead-time, which could cost as much as 1% in efficiency. a 1a schottky is generally a good size for 4a regulators due to the relatively small average current. larger diodes can result in additional transition losses due to their larger junction capacitance. the diode may be omitted if the efficiency loss can be tolerated. calculating ic operating current this section shows how to use the values supplied in the electrical characteristics table to estimate operating cur- rent for a given application. applicatio s i for atio wu uu the total ic operating current through dcin when ac is present and batteries are charging (i dcin_chg ) is given by: i dcin_chg = i ch1 + i vcc2_ac1 + i safety1 + i safety2 + i vlim + i ilim + i smb + i smb_bat1 + i smb_bat2 + i smbalert where: i ch1 is defined in electrical characteristics. i vcc2_ac1 is defined in electrical characteristics. i safetyx is the current used to test the battery thermistor connected to safety1 or safety2. for thermistors that are over-range: i safetyx = 2/64 ? v vcc2 /(rxb + r thx ) for thermistors that are cold-range: i safetyx = 4/64 ? v vcc2 /(rxb + r thx ) for thermistors that are ideal-range: i safetyx = 4/64 ? v vcc2 /(rxb + r thx ) + 2/64 ? v vcc2 / (r1a +r thx ) for thermistors that are hot-range: i safetyx = 4/64 ? v vcc2 /(rxb + r thx ) + 4/64 ? v vcc2 / (r1a +r thx ) r thx is the impedance of the batterys thermistor to ground. rxb = 54.9k rxa = 1.13k sample calculation of i safetyx with v vcc2 = 5.2v thermistor impedance thermistor range i safetyx ( m a) r thx ( w ) 100k over_range 1.05 3.3k ideal_range 42.2 400 under_range 218 i vlim = v vcc2 /(r vlimit + r lim_pu ). i ilim = v vcc2 /(r ilimit + r lim_pu ). r lim_pu is the typical pull-up impedance at v limit and i limit. r lim_pu = 34k. r vlimit is the value of the resistance from v limit to gnd.
ltc1760 36 sn1760 1760is r ilimit is the value of the resistance from i limit to gnd. i smb is the current used for communicating with the smbus host and depends on the amount of bus traffic. i smb_batx is the current used for communicating with battery1 or battery2. i smb_batx = 350 m a ? 0.0155 = 5.425 m a. i smbalert is defined in electrical characteristics. sample calculation of i dcin_chg with two li-ion batteries (r thx = 400), r vlimit = r ilimit = 30k, v cc2 = 5.2v, and no smbus host communication: i dcin_chg =i ch1 + i vcc2_ac1 + i safety1 + i safety2 + i vlim + i ilim + i smb + i smb_bat1 + i smb_bat2 + i smbalert = 1.3ma + 700 m a + 218 m a + 218 m a +81 m a + 81 m a + 0 m a + 5.4 m a + 5.4 m a + 0 m a = 2.62ma the total operating current through bat1 and bat2 when ac is not present (i bat_noac ) is given by: i bat_noac = i bat + i vcc2_ac0 + i safety1 + i safety2 + i smb + i smb_bat1_ac0 + i smb_bat2_ac0 + i smbalert where: i bat is defined in electrical characteristics. i vcc2_ac0 is defined in electrical characteristics. i safetyx is the current used to test the battery thermistor connected to safety1 or safety2. i safetyx = 2/64 ? v vcc2 /(rxb + r thx ). r thx is the impedance of the batterys thermistor to ground. rxb = 54.9k. sample calculation of i safety with v vcc2 = 5.2v thermistor impedance thermistor range i safetyx ( m a) r thx ( w ) 400 under_range 2.9 i smb_batx_aco is the current used for communicat- ing with battery1 or battery2 when ac in not present. i smb_batx_ac0 = 350 m a ? 0.00687 = 2.404 m a. i smb is the current used for communicating with the smbus host and depends on the amount of bus traffic. sample calculation with two li-ion batteries (r thx = 400), v cc2 = 5.2v, and no smbus host communication: i bat_noac C i bat + i vcc2_ac0 + i safety1 + i safety2 + i smb + i smb_bat1_ac0 + i smb_bat2_ac0 + i smbalert = 175 m a + 80 m a + 2.9 m a + 2.9 m a + 0 m a + 2.4 m a + 2.4 m a + 0 m a = 265 m a calculating ic power dissipation the power dissipation of the ltc1760 is dependent upon the gate charge of q tg and q bg .(refer to typical application). the gate charge is determined from the manufacturers data sheet and is dependent upon both the gate voltage swing and the drain voltage swing of the fet. p d = (v dcin C v vcc ) ? f osc ? (q tg + q bg ) + v dcin ? i dcin_chg C v vcc ? (i safety1 + i safety2 ) where: i dcin_chg , i safety1 , i safety2 are defined in the previous section. example: v vcc = 5.2v, v dcin = 19v, f osc = 345khz, q tg = q bg = 15nc, i dcin_chg = 2.62ma, i safety1 = i safety2 = 218 m a. p d = 190mw v set /i set capacitors capacitor c7 is used to filter the delta-sigma modulation frequency components to a level which is essentially dc. acceptable voltage ripple at iset is about 10mv p-p . since the period of the delta-sigma switch closure, t ds , is about 10 m s and the internal idac resistor, r set , is 18.77k, the ripple voltage can be approximated by: d d v vt rc iset ref set = ? 7 applicatio s i for atio wu uu
ltc1760 37 sn1760 1760is input and output capacitors in the 4a lithium battery charger (typical application section), the input capacitor (c in ) is assumed to absorb all input switching ripple current in the converter, so it must have adequate ripple current rating. worst-case rms ripple current will be equal to one half of output charging current. actual capacitance value is not critical. solid tantalum low esr capacitors have high ripple current rating in a relatively small surface mount package, but caution must be used when tantalum capacitors are used for input or output bypass . high input surge currents can be created when the adapter is hot-plugged to the charger or when a battery is connected to the charger. solid tantalum capacitors have a known failure mechanism when subjected to very high turn-on surge currents. only kemet t495 series of surge robust low esr tantalums are rated for high surge conditions such as battery to ground. the relatively high esr of an aluminum electrolytic for c15, located at the ac adapter input terminal, is helpful in reducing ringing during the hot-plug event. refer to an88 for more information. highest possible voltage rating on the capacitor will mini- mize problems. consult with the manufacturer before use. alternatives include new high capacity ceramic (at least 20 m f) from tokin, united chemi-con/marcon, et al. other alternative capacitors include oscon capacitors from sanyo. the output capacitor (c out ) is also assumed to absorb output switching current ripple. the general formula for capacitor current is: i rms = (l1)(f) v bat v dcin () 0.29 (v bat ) 1 applicatio s i for atio wu uu then the equation to extract c7 is: c vt vr ref iset set 7 = ? d d = 0.8/0.01/18.77k(10 m s) @ 0.043 m f in order to prevent overshoot during start-up transients the time constant associated with c7 must be shorter than the time constant of c5 at the i th pin. if c7 is increased to improve ripple rejection, then c5 should be increased proportionally and charger response time to average cur- rent variation will degrade. capacitors c b1 and c b2 are used to filter the vdac delta- sigma modulation frequency components to a level which is essentially dc. c b2 is the primary filter capacitor and cb1 is used to provide a zero in the response to cancel the pole associated with c b2 . acceptable voltage ripple at v set is about 10mv p-p . since the period of the delta-sigma switch closure, t ds , is about 11 m s and the internal vdac resistor, r vset , is 7.2k w , the ripple voltage can be ap- proximated by: d d v vt rcc vset ref vset b b = () ? || 12 then the equation to extract c b1 || c b2 is: cc vt rv bb ref vset vset 12 || = ? d d c b2 should be 10 to 20 c b1 to divide the ripple voltage present at the charger output. therefore c b1 = 0.01 m f and c b2 = 0.1 m f are good starting values. in order to prevent overshoot during start-up transients the time constant associated with c b2 must be shorter than the time constant of c5 at the i th pin. if c b2 is increased to improve ripple rejection, then c5 should be increased proportionally and charger response time to voltage variation will degrade.
ltc1760 38 sn1760 1760is for example: v dcin = 19v, v bat = 12.6v, l1 = 10 m h, and f = 300khz, i rms = 0.41a. emi considerations usually make it desirable to minimize ripple current in the battery leads, and beads or inductors may be added to increase battery impedance at the 300khz switching frequency. switching ripple current splits be- tween the battery and the output capacitor depending on the esr of the output capacitor and the battery imped- ance. if the esr of c out is 0.2 w and the battery impedance is raised to 4 w with a bead or inductor, only 5% of the current ripple will flow in the battery. power path and charge mux mosfet selection three pairs of p-channel mosfets must be used with the wall adapter and the two battery discharge paths. two pairs of n-channel mosfets must be used with the battery charge path. the nominal gate drive levels are set by the clamp drive voltage of their respective control circuitry. this voltage is typically 6.25v. consequently, logic-level threshold mosfets must be used. pay close attention to the b vdss specification for the mosfets as well; many of the logic level mosfets are limited to 30v or less. selection criteria for the power mosfets include the on resistance r ds(on) , input voltage and maximum output current. for the n-channel charge path, the maximum current is the maximum programmed current to be used. for the p-channel discharge path maximum current typi- cally occurs at end of life of the battery when using only one battery. the upper limit of r ds(on) value is a function of the actual power dissipation capability of a given mosfet package that must take into account the pcb layout. as a starting point, without knowing what the pcb dissipation capability would be, derate the package power rating by a factor of two. r p i ds on max mosfet max () = () 2 2 if you are using a dual mosfet package with both mosfets in series, you must cut the package power rating in half again and recalculate. r p i ds on max mosfetdual max () = () 4 2 if you use identical mosfets for both battery paths, voltage drops will track over a wide current range. the ltc1760 linear 25mv cv drop regulation will not occur until the current has dropped below: i mv r linearmax ds on max = 25 2 () however, if you try to use the above equation to determine r ds(on) to force linear mode at full current, the mosfet r ds(on) value becomes unreasonably low for mosfets available at this time. the need for the ltc1760 voltage drop regulation only comes into play for parallel battery configurations that terminate charge or discharge using voltage. at first this seems to be a problem, but there are several factors helping out: 1. when batteries are in parallel current sharing, the current flow through any one battery is less than if it is running stand-alone. 2. most batteries that charge in constant voltage mode, such as li-ion, charge terminate at a current value of c/10 or less which is well within the linear operation range of the mosfets. 3. voltage tracking for the discharge process does not need such precise voltage tracking values. applicatio s i for atio wu uu
ltc1760 39 sn1760 1760is the ltc1760 has two transient conditions that force the discharge path p-channel mosfets to have two additional parameters to consider. the parameters are gate charge q gate and single pulse power capability. when the ltc1760 senses a low_power event, all the p-channel mosfets are turned on simultaneously to allow voltage recovery due to a loss of a given power source. however, there is a delay in the time it takes to turn on all the mosfets. slow mosfets will require more bulk capacitance to hold up all the systems power supply function during the transition and fast mosfet will require less bulk capacitance. the transition speed of a mosfet to an on or off state is a direct function of the mosfet gate charge. t = q gate /i drive i drive is the fixed drive current into the gate from the ltc1760 and t is the time it takes to move that charge to a new state and change the mosfet conduction mode. hence time is directly related to q gate . since q gate goes up with mosfets of lower r ds(on) , choosing such mosfets has a counterproductive increase in gate charge making the mosfet slower. please note that the ltc1760 recovery time specification only refers to the time it takes for the voltage to recover to the level just prior to the low_power event as opposed to full voltage. the single pulse current rating of mosfet is important when a short-circuit takes place. the mosfet must survive a 15ms overload. mosfets of lower r ds(on) or mosfets that use more powerful thermal packages will have a high power surge rating. using too small of a pulse rating will allow the mosfet to blow to the open circuit condition instantly like a fuse. typically there is no outward sign of failure because it happens so fast. please measure the surge current for all discharge power paths under worse case conditions and consult the mosfet data sheet for the limitations. voltage sources with the highest voltage and the most bulk capacitance are often the biggest risk. specifically the mosfets in the wall adapter path with wall adapters of high voltage, large bulk capacitance and low resistance dc cables between the adapter and device are the most common failures. remember to only use the real wall adapter with a produc- tion dc power cord when performing the wall adapter path test. the use of a laboratory power supply is unrealistic for this test and will force you to over specify the mosfet ratings. a battery pack usually has enough series resis- tance to limit the peak current or are too low in voltage to create enough instantaneous power to damage their re- spective power path mosfets. conditioning systems with large loads in systems where the load is too large to be used for conditioning a single battery it may be necessary to bypass the built in calibrate function and simply switch in an external load. a convenient way to accomplish this task is by using an smbus based ltc1623 load switch control- ler. see figure 10. applicatio s i for atio wu uu figure.10 powerpath mux ltc1760 charge mux ltc1623 smbus smbus to/from host to load conditioning load 1760 f10
ltc1760 40 sn1760 1760is applicatio s i for atio wu uu 1760 f10 v bat l1 v in high frequency circulating path bat switch node c in c out d1 figure 11. high-speed switching path csp 1760 f11 direction of charging current r sns csn figure 12. kelvin sensing of charging current pcb layout considerations for maximum efficiency, the switch node rise and fall times should be minimized. to prevent magnetic and electrical field radiation and high frequency resonant prob- lems, proper layout of the components connected to the ic is essential. (see figure 11.) here is a pcb layout priority list for proper layout. layout the pcb using this specific order. 1. input capacitors need to be placed as close as possible to switching fets supply and ground connections. short- est copper trace connections possible. these parts must be on the same layer of copper. vias must not be used to make this connection. 2. the control ic needs to be close to the switching fets gate terminals. keep the gate drive signals short for a clean fet drive. this includes ic supply pins that connect to the switching fet source pins. the ic can be placed on the opposite side of the pcb relative to above. 3. place inductor input as close as possible to switching fets output connection. minimize the surface area of this trace. make the trace width the minimum amount needed to support currentno copper fills or pours. avoid run- ning the connection using multiple layers in parallel. minimize capacitance from this node to any other trace or plane.
ltc1760 41 sn1760 1760is applicatio s i for atio wu uu 4. place the output current sense resistor right next to the inductor output but oriented such that the ics current sense feedback traces going to resistor are not long. the feedback traces need to be routed together as a single pair on the same layer at any given time with smallest trace spacing possible. locate any filter component on these traces next to the ic and not at the sense resistor location. 5. place output capacitors next to the sense resistor output and ground. 6. output capacitor ground connections need to feed into same copper that connects to the input capacitor ground before tying back into system ground. general rules 7. connection of switching ground to system ground or internal ground plane should be single point. if the system has an internal system ground plane, a good way to do this is to cluster vias into a single star point to make the connection. 8. route analog ground as a trace tied back to ic ground (analog ground pin if present) before connecting to any other ground. avoid using the system ground plane. cad trick: make analog ground a separate ground net and use a 0 w resistor to tie analog ground to system ground. 9. a good rule of thumb for via count for a given high current path is to use 0.5a per via. be consistent. 10. if possible, place all the parts listed above on the same pcb layer. 11. copper fills or pours are good for all power connec- tions except as noted above in rule 3. you can also use copper planes on multiple layers in parallel toothis helps with thermal management and lower trace induc- tance improving emi performance further. 12. for best current programming accuracy provide a kelvin connection from r sense to csp and bat. see figure 12 as an example. it is important to keep the parasitic capacitance on the r t , csp and bat pins to a minimum. the traces connecting these pins to their respective resistors should be as short as possible. important safety notes although every effort is made to meet and exceed all required smbus charger v1.1 safety features it is the responsibility of the battery pack to protect itself from excessive currents or voltages. the ltc1760 is not itself a safety device. consult your battery pack manufacture for more information.
ltc1760 42 sn1760 1760is 36 41 3 2 16 37 47 48 46 45 13 40 24 25 29 18 22 20 33 32 26 cb1, 0.1 f cb2 0.47 f c3 0.012 f r6 100 r7 49.9k r5 1.21k r4 12.7k c5 0.15 f cl 20 f c7 0.1 f r9 3.3k d4 c13 0.1 f 1 7 6 9 8 11 10 5 4 12 34 35 14 15 42 43 44 39 38 28 27 17 21 30 31 19 23 c4, 0.22 f qbg qtg l1 10 h r sense 0.025 c in 20 f c out 20 f r1 4.99k r2 280k r3 49.9k r cl 0.03 r sc 0.02 v in smbalert scl sda v dds r11 1k c1 0.1 f c8, 1 f q1 q2 q6 q5 q7 q8 q4 si6928 q3 si6928 1760 ta02 load q9 si6928 q10 si6928 c12 1000pf c1 0.1 f c9, 0.1 f c6 4.7 f r10, 100 clp dc in bat1 bat2 dcdiv comp1 gch2 sch2 gch1 sch1 v set v cc v ss v cc2 smbalert scl sda v dds v limit i limit mode ltc1760 v plus gdci gdco gb1i gb1o gb2i gb2o scp scn lopwr csn csp i th i set sw boost tgate bgate pgnd th2a th2b scl2 sda2 th1a th1b scl1 sda1 bat2 bat1 bat2 bat1 i5 i6 d3 d2 th scl sda th scl sda r2b, 54.9k r2a, 1.13k r2b, 54.9k r2a, 1.13k c11 1800pf r vlimit 10k d1 safety 2 safety 1 d1: mbr130t3 d2: in4148 type q1, q2, q5, q6, q7, q8: si4925dy q3, q4, q9, q10, qtg, qbg: fds6912a powerpath mux r pu r pu v dds charge mux application for a dual battery system (12.6v/4a) typical applicatio u
ltc1760 43 sn1760 1760is package descriptio u fw package 48-lead plastic tssop (6.1mm) (reference ltc dwg # 05-08-1651) fw48 tssop 0502 0.09 ?0.20 (.0035 ?.008) 0 ?8 0.45 ?0.75 (.018 ?.029) 0.17 ?0.27 (.0067 ?.0106) 0.50 (.0197) bsc 6.0 ?6.2** (.236 ?.244) 7.9 ?8.3 (.311 ?.327) 134 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 12.4 ?12.6* (.488 ?.496) 1.20 (.0473) max 0.05 ?0.15 (.002 ?.006) 2 48 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 47 c .10 -t- -c- millimeters (inches) dimensions do not include mold flash. mold flash shall not exceed .152mm (.006") per side dimensions do not include interlead flash. interlead flash shall not exceed .254mm (.010") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale * ** 0.32 0.05 0.50 typ 6.2 0.10 8.1 0.10 recommended solder pad layout 0.95 0.10
ltc1760 44 sn1760 1760is linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear.com ? linear technology corporation 2003 lt/tp 0503 1k ? printed in usa related parts part number description comments lt1571 1.5a switching regulator battery charger 500khz or 200khz switching frequency for small design ltc1733 li-ion linear charger with thermal regulation will not overheat, standalone charger, complete charger lt1769 2a switching regulator battery charger monolithic, 20-lead tssop, 28-lead ssop packages ltc1960 dual battery charger/selector with spi 11-bit v dac , 0.8% voltage accuracy, 10-bit i dac for 5% current accuracy ltc4006 small, high efficiency, fixed voltage, constant current/ constant voltage switching regulator lithium-ion battery charger with termination timer; ac adapter current limit and safetysignal sensor in a small 16 pin package ltc4007 high efficiency, programmable voltage complete charger for 3- or 4-cell lithium-ion batteries, battery charger with termination ac adapter current limit, safetysignal sensor and indicator outputs ltc4008 high efficiency, programmable voltage/ constant current/ constant voltage switching regulator; current battery charger resistor voltage/current programming, ac adapter current limit and safetysignal sensor ltc4100 smart battery charger controller smbus rev 1.1 compliant

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